Silicon Laboratories Si5332-AM1 Reference Manual Download Page 40 | Manualshive

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Register Field Name

Address

Base

Bit

Length

R/W/RW

Description

Device Mode

ID0B_INTG

42

0

15

RW

The terms of an a + b/c desired divider set-
ting must be processed into ID0B_INTG,

ID0B_RES, and ID0B_DEN register terms.
INTG = floor(((a*c+b)*128/c) - 512).

READY if divider is

currently driving the

output, else,

READY/ACTIVE

ID0B_RES

44

0

15

RW

res = mod(b*128, c)

ID0B_DEN

46

0

15

RW

den = c

ID0B_SS_ENA

48

0

1

RW

Spread spectrum enable. This is the only
bank configuration field which may be
changed dynamically while the bank is se-
lected as the active bank. Users may freely
enable/disable spread spectrum.

0 = spread spectrum disabled

1 = spread spectrum enabled

ID0B_SS_MODE

48

1

2

RW

Spread spectrum mode.

0 = disabled

1 = center

2 = invalid

3 = down

ID0B_SS_STEP_NUM

49

0

12

RW

Number of frequency steps in one quarter
SSC modulation period, allows for frequen-
cy step every output clock.

ID0B_SS_STEP_INTG

4B

0

12

RW

Divide ratio spread step size.

ID0B_SS_STEP_RES

4C

0

15

RW

Numerator of spread step size error term.

ID1A_INTG

4E

0

15

RW

The terms of an a + b/c desired interpola-
tive divider setting must be processed into
ID1A_INTG, ID1A_RES, and ID1A_DEN
register terms. INTG = floor(((a*c+b)*128/c)
- 512).

READY if divider is

currently driving the

output, else,

READY/ACTIVE

ID1A_RES

50

0

15

RW

res = mod(b*128, c)

ID1A_DEN

52

0

15

RW

den = c

Si5332-AM1/2/3 Automotive Grade Device Reference Manual

Register Map

silabs.com

| Building a more connected world.

Preliminary Rev. 0.1 | 40

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Summary of Contents for Si5332-AM1

Page 1: ...N_1 XB CLKIN_2 nCLKIN_2 CLKIN_3 nCLKIN_3 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 RELATED DOCUMENTS Any Frequency 6 8 12 output programmable clock generators Offered in three different package sizes supporting different combinations of output clocks and user configurable hardware input pins 32 pin QFN up to 6 outputs 40 pin QFN up to 8 outputs 48 pin QFN up to 12 outputs plann...

Page 2: ... Terminations 12 5 2 AC Coupled Output Clock Terminations 16 6 Programming the Volatile Memory Registers 17 6 1 Programming the PLL 18 6 2 Programming the Clock Path 21 6 3 Programming the Output Clock Frequency 23 6 4 Programming the Output Clock Format 25 6 5 Programming for Frequency Select Operations 27 6 6 Programming Spread Spectrum 28 7 Si5332 Pinout and Package Variant 30 8 Recommended Sch...

Page 3: ...r the integer dividers but the ratios must be integer related CBPro supports the configuration and use of A and B divider sets Spread spectrum is available for any clock output sourced from the Multisynth dividers and is available for use in EMI sensitive applications such as PCI Express The 2 wire I2C bus can be used to control and configure the Si5332 Alternatively some device features can be co...

Page 4: ...evice power up sequencing and expected device behavior Note that a blank unconfigured part will stop and wait to be configured with outputs disabled Outputs available and stable Time system time delay for PLL clock Time system time delay for Oscillator startup Time system time delay for input clock availability Program Si5332 volatile memory with a frequency plan Time system time delay for NVM dow...

Page 5: ...4 in the Si5332 Data Sheet for crystal specifications when selecting a crystal Note that the external crystal specifications in Si5332 Data Sheet must be met A list of recom mended AEC Q200 qualified crystals for the Si5332 can be found in the Silicon Labs document Recommended Crystal Reference Manual for Si5332 Si5357 and Si5225x Automotive Grade Clock Generators Figure 3 1 External Crystal Conne...

Page 6: ...ng CBPro 0 1 µF 0 1 µF Controlled Impedance VDD Core CLKIN_x Figure 3 3 AC Coupled Differential Input Clock LVDS LVPECL HCSL CML etc Controlled Impedance VDD Core CLKIN_x Figure 3 4 DC Coupled Differential Input Clock To determine if a specific DC coupled differential input clock arrangement is supported refer to the table below Table 3 1 Si5332 Input Clock Coupling Restrictions AC or DC Format VD...

Page 7: ...ng group of VDD supply pins VDD_DIG VDDA and VDD_XTAL The Input clock format ter mination is dependent on the driver format used and is usually specified by the driving device and or industry standard clock format specification For example in the case of using a LVCMOS input clock the driving device may recommend a series termination resistor When using LVCMOS input clocks the Si5332 input must be...

Page 8: ...equired CL can be matched by adding capacitance to the external stray CLSEXT and internal device capacitance CLSINT to match the crystal s requirements A value for CLVAR must be se lected such that Required Crystal CL CL VAR CL SINT CL SEXT Or rearranged CL VAR Crystal CL CL SINT CL SEXT Equation 1 Note the required Crystal CL must be greater than or equal to the total stray capacitance quantity C...

Page 9: ...0 Register xosc_ctrim_xin Round to nearest integer CLXA 0 485 Register xosc_ctrim_xout Round to nearest integer CLXB 0 485 If 30 555 pF CLXA XB 38 395 pF then Register xosc_cint_ena 1 Register xosc_ctrim_xin Round to nearest integer CLXA 7 84 0 485 Register xosc_ctrim_xout Round to nearest integer CLXB 7 84 0 485 To summarize use Equation 3 to calculate CLXA CLXB then use the above set of formulas...

Page 10: ... using customized Si5332 orderable part numbers OPN generated through CBPro and then either factory programmed or field programmed using the CBPro Field Programming Don gle GPIO pin functionality can be evaluated tested on a Si5332 EVB by downloading a valid CBPro configuration into the EVB and asserting the GPIO pins on the EVB New GPIO configurations or changes to existing GPIO configurations ar...

Page 11: ...e output impedance of the CMOS driver 25Ω 50Ω Table 5 2 OUTx_Mode vs Output Formats OUTx_MODE Driver Mode 0 off 1 CMOS on positive output only 2 CMOS on negative output only 3 dual CMOS outputs 4 2 5V 3 3V LVDS 5 1 8V LVDS 6 2 5V 3 3V LVDS fast 7 1 8V LVDS fast 8 HCSL 50 Ω external termination 9 HCSL 50 Ω internal termination 10 HCSL 42 5 Ω external termination 11 HCSL 42 5 Ω internal termination ...

Page 12: ...Figure 5 1 LVCMOS Termination Option 1 Set output driver to 25 Ω mode 1 43 V to 3 46 V OUTx OUTx Zo 50 Ω Zo 50 Ω Rs Rs Rs Zo Rdrv Figure 5 2 LVCMOS Termination Option 2 Si5332 AM1 2 3 Automotive Grade Device Reference Manual Output Clock Terminations silabs com Building a more connected world Preliminary Rev 0 1 12 ...

Page 13: ...st Termination Option 1 LVDS driver 1 71 V to 3 46 V OUTx OUTx Zo RT 2 Zo RT 2 LVDS receiver RT 2 RT 2 Figure 5 4 LVDS LVDS Fast Termination Option 2 Si5332 AM1 2 3 Automotive Grade Device Reference Manual Output Clock Terminations silabs com Building a more connected world Preliminary Rev 0 1 13 ...

Page 14: ...mination Option 1 VDD Standard Resistance Resistance Value 2 5 R1 250 R2 62 5 3 3 R1 125 R2 84 LVPECL driver 2 25 V to 3 46 V OUTx OUTx Zo 50 Ω Zo 50 Ω LVPECL receiver R1 R2 R3 Figure 5 6 LVPECL Termination Option 2 Si5332 AM1 2 3 Automotive Grade Device Reference Manual Output Clock Terminations silabs com Building a more connected world Preliminary Rev 0 1 14 ...

Page 15: ...5 Ω or 50 Ω HCSL receiver Zo 42 5 Ω or 50 Ω Figure 5 7 HCSL Internal Termination Mode HCSL driver 1 71 V to 3 46 V OUTx OUTx Zo 42 5 Ω or 50 Ω HCSL receiver Zo 42 5 Ω or 50 Ω RT Zo RT Zo Figure 5 8 HCSL External Termination Mode Si5332 AM1 2 3 Automotive Grade Device Reference Manual Output Clock Terminations silabs com Building a more connected world Preliminary Rev 0 1 15 ...

Page 16: ... 50 Ω 0 1 µF 100 Ω Figure 5 11 LVDS Termination The terminations shown in Figure 5 3 LVDS LVDS Fast Termination Option 1 on page 13 through Figure 5 6 LVPECL Termination Option 2 on page 14 can also be converted by adding DC blocking capacitances right before the receiver pins However the recom mendation shown in Figure 5 11 LVDS Termination on page 16 is the simplest way to realize AC coupling i ...

Page 17: ...sary to realize a PLL function a clock output to clock input relationship and can be used to monitor input clock that controls the PLL The top level block diagram is repeated here to refresh the various limits and possibilities that are necessary for the calculations below P PFD LF Mn Md R R R R R R R R R R R R 1 63 VDD_XTAL VDDA VDDOA VDDOB VDDOC VDDOD VDDOE XA CLKIN_1 XB CLKIN_2 nCLKIN_2 CLKIN_3...

Page 18: ...e frequency the PLL can tolerate vcoCenterFreq 2 5 GHz The center frequency of the VCO s tuning range vcoMinFreq 2 375 GHz The minimum frequency of the VCO s tuning range vcoMaxFreq 2 625 GHz The maximum frequency of the VCO s tuning range List all required output frequencies Fxy in groups denoted by Gx where x 0 1 2 3 4 5 and y a b c This grouping is done such that frequencies related to each oth...

Page 19: ...e broken down into the following steps 1 From the output frequency set form a set of M non equal frequencies Group the N M equal frequencies into the same x in Foutxy grouping 2 Now form MC2 groups of M 2 output frequencies Find the LCM of each group and find an integer I that can such that a vcoFreq I LCM can meet the constraint for vcoFreq in Table 6 1 Constraints for PLL Reference Frequency and...

Page 20: ...gister field value that will enable that loop BW setting Table 6 4 Loop BW Options PLL_MODE Loop Bandwidth kHz PLL Ref Freq Min MHz PLL Ref Freq Max MHz 0 ILLEGAL IF PLL MODE IS ENA BLED 1 350 10 15 2 250 10 15 3 175 10 15 4 500 15 30 5 350 15 30 6 250 15 30 7 175 15 30 8 500 30 50 9 350 30 50 10 250 30 50 11 175 30 50 This algorithm will result in a final solution for a VCO frequency vcoFreq that...

Page 21: ... to be followed by those applications that wish to achieve the highest possible levels of jitter performance Because CMOS outputs have large pk pk swings and do not present a balanced load to the VDDO supplies CMOS outputs generate much more crosstalk than differential outputs For this reason CMOS outputs should be avoided whenever possible When CMOS is unavoidable even greater care must be taken ...

Page 22: ...ES and IDPA_DEN IDxA_INTG floor 128 vcoFreq Foutxa Rxa IDxA_RES IDxA_DEN 128 vcoFreq Foutxa Rxa IDxA_INTG Si5332 AM1 2 3 Automotive Grade Device Reference Manual Programming the Volatile Memory Registers silabs com Building a more connected world Preliminary Rev 0 1 22 ...

Page 23: ...disabled 1 63 divide value R1B OUT2_DIV Driver divider ratio 0 disabled 1 63 divide value R2A OUT3_DIV Driver divider ratio 0 disabled 1 63 divide value R2B OUT4_DIV Driver divider ratio 0 disabled 1 63 divide value R2C OUT5_DIV Driver divider ratio 0 disabled 1 63 divide value R3A OUT6_DIV Driver divider ratio 0 disabled 1 63 divide value R3B OUT7_DIV Driver divider ratio 0 disabled 1 63 divide v...

Page 24: ...ider ratio 0 disabled 1 63 divide value R5B OUT11_DIV Driver divider ratio 0 disabled 1 63 divide value Si5332 AM1 2 3 Automotive Grade Device Reference Manual Programming the Volatile Memory Registers silabs com Building a more connected world Preliminary Rev 0 1 24 ...

Page 25: ...CMOS mode 0 no inversion 1 OUTx inverted OUTx _cmos_slew Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 slower 11 slowest OUTx _cmos_str CMOS output impedance control 0 50 Ω 1 25 Ω Table 6 8 Driver Mode Options drvxy_MODE Driver Mode 0 off 1 CMOS on positive output only 2 CMOS on negative output only 3 dual CMOS outputs 4 2 5 V 3 3 V LVDS 5 1 8 V LVDS 6 2 5 V 3 3 V LVDS fast 7 1 8...

Page 26: ... Driver Mode 13 Reserved 14 Reserved 15 Reserved Si5332 AM1 2 3 Automotive Grade Device Reference Manual Programming the Volatile Memory Registers silabs com Building a more connected world Preliminary Rev 0 1 26 ...

Page 27: ...ID once ID0_CFG 1 thus changing the ID from bank A to bank B Spread spectrum enable fields ID0A_SS_ENA and ID0B_SS_ENA are the only exception and may be enabled disabled while bank is selected 0 bank A 1 bank B In a factory programmed part a pin the FS pin can be used for the same purpose as the control registers Once a control bit is set the backup divider values control the output frequency and ...

Page 28: ... idxy_ss_step_num vcoFreq idxy Fmod 4 idxy_ss_step_res Amod idxy_den idxy 128 2 idxy_ss_step_num Figure 6 2 Center and Down Spread SSC Clocks as Frequency vs Time The table below shows the register fields and terms idxy_ss_step_num and idxy_ss_step_res idxy_ss_step_num is the number of frequency steps between the mean and the maximum minimum frequencies in SSC clocking and idxy_ss_step_res is the ...

Page 29: ...dxy_ss_step_den Denominator of spread step size error term To enable SSC idxy_ss_ena needs to be set and the right mode selected in idxy_ss_mode The number of output clocks in each frequency step idxy_ss_clk_num needs to be set to 1 and idxy_ss_step_den is the same as idxy_den and idxy_ss_step_intg is always zero The following flow needs to be followed to program the registers into Si5332 1 Write ...

Page 30: ...s The pinout for each is shown in the figures below Figure 7 1 12 Output Si5332 7x7 mm QFN Package Note Planned future product not yet released Si5332 AM1 2 3 Automotive Grade Device Reference Manual Si5332 Pinout and Package Variant silabs com Building a more connected world Preliminary Rev 0 1 30 ...

Page 31: ...332 6x6 mm QFN Package Figure 7 3 6 Output Si5332 5x5 mm QFN Package Si5332 AM1 2 3 Automotive Grade Device Reference Manual Si5332 Pinout and Package Variant silabs com Building a more connected world Preliminary Rev 0 1 31 ...

Page 32: ...an be noise due to some oscillatory behavior from an LDO regulator ii The only filtering needed on each supply node is a 1 μF and a 0 1 μF placed as close as possible to that node iii The Si5332 EVBs have a much larger capacitance on the regulator end mainly to compensate for the regulator loop so that there is no oscillatory behavior from the regulators regardless of the voltage supply value set ...

Page 33: ...ccessed Si5332 has two modes of function READY where the Si5332 is ready for programming in which time there will no outputs from Si5332 and ACTIVE where the Si5332 is actively locked to an input and is providing outputs Some register fields can be programmed in either READY or ACTIVE mode READY ACTIVE whereas others can only be programmed in READY mode READY Device mode provides input on which mo...

Page 34: ...OPN ID 4 Example For Si5332AD98765 AM1 ID 4 9 FACTORY_OPN_RE VISION 12 4 4 R The Orderable part number s product revi sion number DESIGN_ID0 17 0 8 R Design identification set by user in CBPro project file READY ACTIVE DESIGN_ID1 18 0 8 R DESIGN_ID2 19 0 8 R I2C_ADDR 21 0 7 R I2C mode device address Reset value is 110_1010 binary I2C_SCL_PUP_ENA 23 0 1 RW Enable 50 kΩ pullup resistor on SCL pad RE...

Page 35: ...t buffer CLKIN_2 3 Clock from input buffer CLKIN_3 READY ACTIVE OMUX1_SEL1 26 4 3 RW Selects output mux clock source for output clocks in group G1 OUT1 for AM1 AM2 0 HSDIV0 1 HSDIV1 2 HSDIV2 3 HSDIV3 4 HSDIV4 5 ID0 6 ID1 7 Clock from OMUX1_SEL0 Note that the OMUX1_SEL1 value is forced to 7 whenever the PLL is disabled READY ACTIVE OMUX2_SEL0 27 0 2 RW Selects output mux clock source for output clo...

Page 36: ... from input buffer CLKIN_2 3 Clock from input buffer CLKIN_3 READY ACTIVE OMUX3_SEL1 28 4 3 RW Selects output mux clock source for output clocks in group G3 OUT3 for AM1 OUT4 OUT5 for AM2 0 HSDIV0 1 HSDIV1 2 HSDIV2 3 HSDIV3 4 HSDIV4 5 ID0 6 ID1 7 Clock from OMUX3_SEL0 Note that the OMUX3_SEL1 value is forced to 7 whenever the PLL is disabled READY ACTIVE OMUX4_SEL0 29 0 2 RW Selects output mux clo...

Page 37: ...KIN_2 3 Clock from input buffer CLKIN_3 READY ACTIVE OMUX5_SEL1 2A 4 3 RW Selects output mux clock source for output clocks in group G5 OUT5 for AM1 OUT7 for AM2 0 HSDIV0 1 HSDIV1 2 HSDIV2 3 HSDIV3 4 HSDIV4 5 ID0 6 ID1 7 Clock from OMUX5_SEL0 Note that the OMUX5_SEL1 value is forced to 7 whenever the PLL is disabled READY ACTIVE HSDIV0A_DIV 2B 0 8 RW O0 divider value READY if divider is currently ...

Page 38: ... Spread spectrum enable fields ID0A_SS_ENA and ID0B_SS_ENA are the only exception and may be enabled disabled while bank is selected 0 bank A 1 bank B READY ACTIVE HSDIV4_DIV_SEL 35 4 1 RW Selects bank A 0 or bank B 1 O4 divider settings Same description applies as for HSDIV0_DIV_SEL READY ACTIVE ID1_CFG_SEL 35 7 1 RW N1 configuration bank select Same de scription related to ID1 applies as in the ...

Page 39: ...ile the bank is se lected as the active bank Users may freely enable disable spread spectrum 0 spread spectrum disabled 1 spread spectrum enabled READY if divider is currently driving the output else READY ACTIVE ID0A_SS_MODE 3C 1 2 RW Spread spectrum mode 0 disabled 1 center 2 invalid 3 down ID0A_SS_STEP_NUM 3D 0 12 RW Number of frequency steps in one quarter SSC modulation period allows for freq...

Page 40: ... spread spectrum enabled ID0B_SS_MODE 48 1 2 RW Spread spectrum mode 0 disabled 1 center 2 invalid 3 down ID0B_SS_STEP_NUM 49 0 12 RW Number of frequency steps in one quarter SSC modulation period allows for frequen cy step every output clock ID0B_SS_STEP_INTG 4B 0 12 RW Divide ratio spread step size ID0B_SS_STEP_RES 4C 0 15 RW Numerator of spread step size error term ID1A_INTG 4E 0 15 RW The term...

Page 41: ...d interpola tive divider setting must be processed into ID1A_INTG ID1A_RES and ID1A_DEN register terms INTG floor a c b 128 c 512 READY if divider is currently driving the output else READY ACTIVE ID1B_RES 5C 0 15 RW res mod b 128 c ID1B_DEN 5E 0 15 RW den c ID1B_SS_ENA 60 0 1 RW Spread spectrum enable This is the only bank configuration field which may be changed dynamically while the bank is se ...

Page 42: ... NVM READY PLL_MODE BE 2 4 RW Sets PLL BW See Table 6 1 Constraints for PLL Reference Frequency and VCO Fre quency on page 18 READY XOSC_CINT_ENA BF 7 1 RW Enables a fixed 7 84 pf of internal loading capacitance to values set by XOSC_CTRIM_XA XB registers Refer to Section 3 2 Calculating Crystal Loading Ca pacitance for information on use of this reg ister READY XOSC_CTRIM_XA C0 0 6 RW Load capaci...

Page 43: ...dual CMOS mode 0 no inversion 1 OUT0b inverted READY OUT0_CMOS_SLEW 7E 0 2 RW Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 slower 11 slowest READY OUT0_CMOS_STR 7E 2 1 RW CMOS output impedance control 0 50 Ω 1 25 Ω READY OUT1_MODE 7F 0 4 RW Software interpreted driver configu ration See Table 6 7 Driver Set Up Options on page 25 READY OUT1_DIV 80 0 6 RW Driver divider ratio 0 di...

Page 44: ...IV 8A 0 6 RW Driver divider ratio 0 disabled 1 63 divide value READY OUT2_SKEW 8B 0 3 RW Skew control Programmed as an unsigned integer Can add delay of 35 ps step up to 280 ps READY OUT2_STOP_HIGHZ 8C 0 2 RW Driver output state when stopped 0 low Z 1 high Z READY OUT2_CMOS_INV 8C 4 1 RW Sets the polarity of the two outputs in dual CMOS mode 0 no inversion 1 OUT2b inverted READY OUT2_CMOS_SLEW 8D ...

Page 45: ...RW Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 slower 11 slowest READY OUT3_CMOS_STR 9C 2 1 RW CMOS output impedance control 0 50 Ω 1 25 Ω READY OUT4_MODE A7 0 4 RW Software interpreted driver configu ration See Table 6 7 Driver Set Up Options on page 25 READY OUT4_DIV A8 0 6 RW Driver divider ratio 0 disabled 1 63 divide value READY OUT4_SKEW A9 0 3 RW Skew control Programmed ...

Page 46: ...r output state when stopped 0 low Z 1 high Z READY OUT5_CMOS_INV AF 4 1 RW Sets the polarity of the two outputs in dual CMOS mode 0 no inversion 1 OUT5b inverted READY OUT5_CMOS_SLEW B0 0 1 RW Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 slower 11 slowest READY OUT5_CMOS_STR B0 2 1 RW CMOS output impedance control 0 50 Ω 1 25 Ω READY OUT2_OE B6 3 1 RW Output enable control for O...

Page 47: ...T4 READY ACTIVE CLKIN_2_CLK_SEL 73 0 2 RW 0 disabled 1 differential 2 CMOS DC 3 CMOS AC READY IMUX_SEL 24 0 2 RW Selects input mux clock source 0 Disabled 1 XOSC 2 CLKIN_2 3 Disabled READY Si5332 AM1 2 3 Automotive Grade Device Reference Manual Register Map silabs com Building a more connected world Preliminary Rev 0 1 47 ...

Page 48: ...dual CMOS mode 0 no inversion 1 OUT0b inverted READY OUT0_CMOS_SLEW 7E 0 2 RW Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 slower 11 slowest READY OUT0_CMOS_STR 7E 2 1 RW CMOS output impedance control 0 50 Ω 1 25 Ω READY OUT1_MODE 7F 0 4 RW Software interpreted driver configu ration See Table 6 7 Driver Set Up Options on page 25 READY OUT1_DIV 80 0 6 RW Driver divider ratio 0 di...

Page 49: ...IV 8A 0 6 RW Driver divider ratio 0 disabled 1 63 divide value READY OUT2_SKEW 8B 0 3 RW Skew control Programmed as an unsigned integer Can add delay of 35 ps step up to 280 ps READY OUT2_STOP_HIGHZ 8C 0 2 RW Driver output state when stopped 0 low Z 1 high Z READY OUT2_CMOS_INV 8C 4 1 RW Sets the polarity of the two outputs in dual CMOS mode 0 no inversion 1 OUT2b inverted READY OUT2_CMOS_SLEW 8D ...

Page 50: ...RW Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 slower 11 slowest READY OUT3_CMOS_STR 92 2 1 RW CMOS output impedance control 0 50 Ω 1 25 Ω READY OUT4_MODE 98 0 4 RW Software interpreted driver configu ration See Table 6 7 Driver Set Up Options on page 25 READY OUT4_DIV 99 0 6 RW Driver divider ratio 0 disabled 1 63 divide value READY OUT4_SKEW 9A 0 3 RW Skew control Programmed ...

Page 51: ...5 ps step up to 280 ps READY OUT5_STOP_HIGHZ A0 0 1 RW Driver output state when stopped 0 low Z 1 high Z READY OUT5_CMOS_INV A0 4 1 RW Sets the polarity of the two outputs in dual CMOS mode 0 no inversion 1 OUT5b inverted READY OUT5_CMOS_SLEW A1 0 1 RW Controls CMOS slew rate from fast to slow 00 fastest 01 slow 10 slower 11 slowest READY OUT5_CMOS_STR A1 2 1 RW CMOS output impedance control 0 50 ...

Page 52: ...CMOS_STR AB 2 1 RW CMOS output impedance control 0 50 Ω 1 25 Ω READY OUT7_MODE AC 0 4 RW Software interpreted driver configu ration See Table 6 7 Driver Set Up Options on page 25 READY OUT7_DIV AD 0 6 RW Driver divider ratio 0 disabled 1 63 divide value READY OUT7_SKEW AE 0 3 RW Skew control Programmed as an unsigned integer Can add delay of 35 ps step up to 280 ps READY OUT7_STOP_HIGHZ AF 0 1 RW ...

Page 53: ...VE OUT0_OE B6 0 1 RW Output enable control for OUT0 READY ACTIVE OUT1_OE B6 1 1 RW Output enable control for OUT1 READY ACTIVE OUT7_OE B7 2 1 RW Output enable control for OUT7 READY ACTIVE OUT6_OE B7 1 1 RW Output enable control for OUT6 READY ACTIVE CLKIN_2_CLK_SEL 73 0 2 RW Select the CLKIN_2 input buffer mode 0 disabled 1 differential 2 CMOS DC 3 CMOS AC READY CLKIN_3_CLK_SEL 74 0 2 RW Select t...

Page 54: ... Revision History Revision 0 1 September 20 2019 Initial release Si5332 AM1 2 3 Automotive Grade Device Reference Manual Revision History silabs com Building a more connected world Preliminary Rev 0 1 54 ...

Page 55: ...d circuits The products are not designed or authorized to be used within any FDA Class III devices applications for which FDA premarket approval is required or Life Support Systems without the specific written consent of Silicon Labs A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant...

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