Si5321-EVB
Rev. 0.4
3
and a 0.1
F capacitor, such that the positive and
negative inputs of the differential pair each see a 50
termination to “ac ground,” and the line-to-line
termination impedance is 100
.
For single-ended operation, supply a signal to one of
the differential inputs (usually the positive input). The
other input should be shorted to ground using an SMA
shorting plug. The on-board termination circuit provides
a 50
termination to ac-ground for each leg of the
differential pair.
Differential Clock Output Signals
The differential clock outputs from the Si5321 device
are routed to the perimeter of the circuit board using
50
transmission line structures. The capacitors that
provide ac-coupling are located near the clock output
SMA connectors.
Internal Regulator Compensation
The Si5321-EVB contains pad locations for a resistor
and a capacitor between the VDD25 node and ground.
The resistor pads are populated with a 0
resistor. The
capacitor pads are populated with a low ESR 33
F
tantalum capacitor. This is the suggested compensation
circuit for Si5321 devices.
There are two considerations for selecting this
combination of compensation resistor and capacitor.
First, is the stability of the regulator. The second is noise
filtering.
The acceptable range for the time constant at this node
is 15
s to 50
s. The capacitor used on the board is a
33
F capacitor with an ESR of .8
. This yields a time
constant of 26.4
s. The designer could decide to use a
330
F capacitor with an ESR of .15
. This yields a
time constant of 49.5
s. Each of these cases provide a
compensation circuit that makes the output of the
regulator stable.
The second issue is noise filtering. For this, more
capacitance is usually better. For the two cases
described above, the 330
F case provides greater
noise filtering. However, the large case size of the
330
F capacitor might make it impractical for many
applications. The Si5321 device is specified with the
33
F cap.
Default Jumper Settings
The default jumper settings for the Si5321-EVB board
are given in Table 1. These settings configure the board
for operation from a 3.3 V supply.
Table 1. Si5321-EVB Assembly Rev B-01 Default Jumper/Switch Settings
Location
Signal
State
Notes
JP6
VSEL33
1
Internal Regulator enabled
JP1
VDD33
Open
3.3 V plane not connected to 2.5 V plane
JP5
VALTIME
0
100 ms Validation Time
FEC[0]
0
No FEC scaling
FEC[1]
0
No FEC scaling
FEC[2]
0
No FEC scaling
BWSEL[0]
0
Loop Filter Bandwidth = 800 Hz
BWSEL[1]
1
Loop Filter Bandwidth = 800 Hz
INFRQSEL[0]
1
Clock IN = 19.44 MHz
INFRQSEL[1]
0
Clock IN = 19.44 MHz
INFRQSEL[2]
0
Clock IN = 19.44 MHz
FRQSEL[0]
1
Clock Out = 622.08 MHz
FRQSEL[1]
1
Clock Out = 622.08 MHz
FRQSEL[2]
0
Clock Out = 622.08 MHz
BWBOOST
1
Selected bandwidth not doubled
FXDDELAY
0
Fixed Delay disabled
JP7
LED ENABLE
On
LED Indicators enabled
Summary of Contents for Si5321-EVB
Page 6: ...Si5321 EVB 6 Rev 0 4 Figure 2 Si5321 EVB Top Silkscreen ...
Page 7: ...Si5321 EVB Rev 0 4 7 Figure 3 Si5321 EVB Layer 1 Component Side ...
Page 8: ...Si5321 EVB 8 Rev 0 4 Figure 4 Si5321 EVB Layer 2 High Speed Signals ...
Page 9: ...Si5321 EVB Rev 0 4 9 Figure 5 Si5321 EVB Layer 3 GND ...
Page 10: ...Si5321 EVB 10 Rev 0 4 Figure 6 Si5321 EVB Layer 4 VDD 2 5 ...
Page 11: ...Si5321 EVB Rev 0 4 11 Figure 7 Si5321 EVB Layer 5 GND ...
Page 12: ...Si5321 EVB 12 Rev 0 4 Figure 8 Si5321 EVB Layer 6 VDD 3 3 ...
Page 13: ...Si5321 EVB Rev 0 4 13 Figure 9 Si5321 EVB Layer 7 GND ...
Page 14: ...Si5321 EVB 14 Rev 0 4 Figure 10 Si5321 EVB Layer 8 Bottom ...
Page 15: ...Si5321 EVB Rev 0 4 15 Figure 11 Si5321 EVB Bottom Silkscreen ...
Page 17: ...Si5321 EVB Rev 0 4 17 Notes ...
