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S i 5 3 2 1 - E V B

2

Rev. 0.4

Functional Overview

The Si5321-EVB is the customer evaluation board for
the Si5321 SONET/SDH Precision Port Card Clock IC.
It is supplied to customers for evaluation of the Si5321
device. The board provides access to signals
associated with normal operation of the device and
signals that are reserved for factory testing purposes. 

Power Supply Selection and Connections

The Si5321-EVB board is switch selectable for
operation using either a single 3.3 V or a single 2.5 V
supply. 

For operation using a 3.3 V supply, configure the board
as follows:

1. Remove power supply connections from the VDD and 

GND terminals of the board’s power connector, J3.

2. Remove the connection between VDD33 and VDD25 by 

removing the jumper on header JPI.

3. Set VSEL33 high by sliding the switch on the VSEL33 

(JP6) to the side marked “1”.

4. Connect the power supply ground lead and 3.3 V supply 

lead to the GND and VDD terminals of the board’s power 
connector, J3.

For operation using a 2.5 V supply, configure the board
as follows:

1. Remove power supply connections from the VDD and 

GND terminals of the board’s power connector, J3.

2. Set VSEL33 low by sliding the switch on the VSEL33 (JP6) 

to the side marked “0”.

3. Connect VDD33 and VDD25 by installing a jumper 

between one of the 3.3 V pins and one of the 2.5 V pins on 
header JPI.

4. Connect the power supply ground lead and 2.5 V supply 

lead to the GND and VDD terminals of the board’s power 
connector, J3.

Power Consumption

Typical supply current draw for the Si5321-EVB is
110 mA.

Si5321 Control Inputs

The control inputs to the Si5321 are each routed from
the center pin of a SPDT switch, JP5, to the Si5321
device. Additionally, the switches at JP5 are connected
to GND on one side of the switch and to VDD33 on the
other side. This arrangement allows easy configuration
of each input to either a high or low state. To further
reduce the coupling of noise into the device through
these control inputs, the signals are routed on internal
layers between ground planes.

RSTN/CAL Settings for Normal Operation 
and Self-Calibration

The RSTN/CAL signal is an LVTTL input to the Si5321
and has an on-chip pulldown mechanism. This pin must
be set high for normal operation of the Si5321 device. 

Setting RSTN/CAL low forces the Si5321 into the reset
state. A low-to-high transition of RSTN/CAL enables the
part and initiates a self-calibration sequence. 

The Si5321 device initiates self-calibration at powerup if
the RSTN/CAL signal is held high. A self-calibration of
the device also can be manually initiated by
momentarily pushing the RSTN/CAL switch, SWI and
then releasing. 

Manually initiate self-calibration after changing the state
of either the BWSEL[1:0] control inputs or the FEC[1:0]
inputs. 

Whether manually initiated or automatically initiated at
powerup, the self-calibration process requires a valid
input clock. If the self-calibration is initiated without a
valid clock present, the device waits for a valid clock
before completing the self-calibration. The Si5321 clock
output is set to the lower end of the operating frequency
range while the device waits for a valid clock. After the
clock input is validated, the calibration process runs to
completion, the device locks to the clock input, and the
clock output shifts to its target frequency. Subsequent
losses of the input clock signal do not require re-
calibration. If the clock input is lost after self-calibration,
the device enters Digital Hold mode. When the input
clock returns, the device re-locks to the input clock
without performing a self-calibration.

Status Signals

The status outputs from the Si5321 device are each
routed to one pin of a two-row header. The signals are
arranged so that each signal has a ground pin adjacent
to the signal pin for reference. The row of signal pins is
marked with an “S”, and the row of ground pins is
marked with a “G”.

Visible indicators are added to the LOS and CAL_ACTV
signals. The LEDs glow when the signal is active and
the LED enable switch is set to ON. The LOS LED is
illuminated when the device does not recognize a valid
clock input. The CAL_ACTV LED is illuminated when
the device is calibrating to an input clock.

Differential Clock Input Signals

The differential Clock inputs to the Si5321-EVB board
are ac coupled and terminated on the board at a
location near the SMA input connectors. The
termination components are located on the top side of
the board. The termination circuit consists of two 50

Summary of Contents for Si5321-EVB

Page 1: ...erved for factory testing purposes Features Single supply at either 3 3 or 2 5 V jumper configurable Differential I Os ac coupled on board Differential inputs terminated on board Control input signals are switch configurable Status outputs brought out to headers for easy access Function Block Diagram t e x t t e x t Si5321 CLKIN CLKOUT Control Inputs Status Outputs Control Input Jumper Header Stat...

Page 2: ...and has an on chip pulldown mechanism This pin must be set high for normal operation of the Si5321 device Setting RSTN CAL low forces the Si5321 into the reset state A low to high transition of RSTN CAL enables the part and initiates a self calibration sequence The Si5321 device initiates self calibration at powerup if the RSTN CAL signal is held high A self calibration of the device also can be m...

Page 3: ...node is 15 s to 50 s The capacitor used on the board is a 33 F capacitor with an ESR of 8 This yields a time constant of 26 4 s The designer could decide to use a 330 F capacitor with an ESR of 15 This yields a time constant of 49 5 s Each of these cases provide a compensation circuit that makes the output of the regulator stable The second issue is noise filtering For this more capacitance is usu...

Page 4: ...V_ID 4 NC DEV_ID 5 NC DEV_ID 0 NC DEV_ID 1 NC DEV_ID 2 NC ANAOUT FXDDELAY FRQSEL 2 FEC 2 RES TMOD 0 RES TMOD 1 RES TMOD 2 BWBOOST GND GND GND GND GND GND GND GND GND GND GND GND GND GND CLKIN CLKIN INFRQSEL 0 INFRQSEL 1 INFRQSEL 2 FRQSEL 0 FRQSEL 1 FEC 0 FEC 1 BWSEL 0 BWSEL 1 VALTIME RSTN CAL VSEL33 REXT R9 4 99k 0603 D2 LN1274R R3 49 9 0603 JP6 HEADER 3x2 1 2 3 4 5 6 1 2 3 4 5 6 R8 4 99k 0402 C6 ...

Page 5: ...JP1 14x3 HEADER JP2 JP4 JP5 1x3 HEADER JP3 1x2 HEADER JP6 HEADER 3x2 JP7 5x3 JP8 7x2 Header J1 J2 J3 J4 SMA notch fit Johnson Components 82 SMA S50 0 45 J5 power connector 2 pin Phoenix Contact 140 A 111 02 1729018 L1 600 ohm 1206 MURATA BLM31A601S Q1 Q2 MOS SM FDN337N Fairchild FDN337N R1 0 0603 Venkel CR0603 16W 000T R3 R2 49 9 0603 Venkel CR0603 16W 49R9FT R4 R5 R10 0 0402 Venkel CR0402 16W 000...

Page 6: ...Si5321 EVB 6 Rev 0 4 Figure 2 Si5321 EVB Top Silkscreen ...

Page 7: ...Si5321 EVB Rev 0 4 7 Figure 3 Si5321 EVB Layer 1 Component Side ...

Page 8: ...Si5321 EVB 8 Rev 0 4 Figure 4 Si5321 EVB Layer 2 High Speed Signals ...

Page 9: ...Si5321 EVB Rev 0 4 9 Figure 5 Si5321 EVB Layer 3 GND ...

Page 10: ...Si5321 EVB 10 Rev 0 4 Figure 6 Si5321 EVB Layer 4 VDD 2 5 ...

Page 11: ...Si5321 EVB Rev 0 4 11 Figure 7 Si5321 EVB Layer 5 GND ...

Page 12: ...Si5321 EVB 12 Rev 0 4 Figure 8 Si5321 EVB Layer 6 VDD 3 3 ...

Page 13: ...Si5321 EVB Rev 0 4 13 Figure 9 Si5321 EVB Layer 7 GND ...

Page 14: ...Si5321 EVB 14 Rev 0 4 Figure 10 Si5321 EVB Layer 8 Bottom ...

Page 15: ...Si5321 EVB Rev 0 4 15 Figure 11 Si5321 EVB Bottom Silkscreen ...

Page 16: ... List Revision 0 1 to Revision 0 4 Updated to reflect Rev D printed circuit boards Default jumper settings added Evaluation Board Assembly Revision History Assembly Level PCB Rev Si5321 Rev Assembly Notes B 01 Rev C Rev B Assemble per BOM rev B 01 ...

Page 17: ...Si5321 EVB Rev 0 4 17 Notes ...

Page 18: ...th which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons Tradem...

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