Silicon Laboratories Si5 UC-EVB Series, Manual

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9. Output Clock Terminations
The drawing in the figure below shows the default output termination circuit for CLK1 output of the Si5xxUC-EVB. This default source
termination is for typical 3.3V
LVPECL . CLK2 and CLK3 are also terminated similarly for 3.3V LVPECL. If not using LVPECL, this termi-
nation circuit may require component modification. The following table gives examples of recommended output termination components
for various output formats when using Si51x, Si53x, Si54x, Si55x, Si56x, Si57x, and Si59x devices, but
always refer to the specific
device datasheet and/or appropriate application note for details of required output source termination for the specific device
being evaluated
.
Figure 9.1. CLK1 Output Default Terminations
Table 9.1. Example Output Clock Source Terminations (Si51x, Si53x, Si54x, Si55x, Si56x, Si57x, and Si59x only)
Output Format Series Resistor Position (e.g.,
R4, R6)
Parallel Resistor Position
(e.g., R5, R7)
Series Capacitor Position
(e.g., C3, C5)
LVPECL 3.3V: AC coupled 0 Ω 130 Ω 0.1μF
LVPECL 2.5V: AC coupled 0 Ω 90 Ω 0.1μF
LVPECL: DC coupled 0 Ω Remove replace w/0 Ω
LVDS : AC coupled 0 Ω Remove 0.1μF
LVDS : DC coupled 0 Ω Remove replace w/0 Ω
HCSL 0 Ω Remove replace w/0 Ω
CML 0 Ω Remove 0.1μF
LVCMOS : AC coupled 0 Ω Remove 0.1μF
LVCMOS : DC coupled 0 Ω Remove replace w/10 Ω
UG298: Si5xxUC-EVB
Output Clock Terminations
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