Silicon Laboratories Si4455 Series, Programming Manual

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The API properties are listed in Table 5.
The following sections describe the SPI transactions of sending commands and getting information from the chip.
4.2.1. Sending Commands to a Radio
The behavior of the radio can be changed by sending API commands to the radio (e.g., changing the power states,
start packet transmission, etc.). The radio can be configured through several "properties". The properties represent
radio configuration settings, such as interrupt settings, modem parameters, packet handler settings, etc., and can
be set and read via API commands. For most of the commands, the host MCU does not expect any response from
the radio chip. Other commands are used to read back a property from the chip, such as checking the interrupt
status flags, reading the transmit/receive FIFOs.
After the radio receives a command, it processes the request. During this time, the radio is not capable of receiving
a new command. The host MCU must identify when the next command can be sent. The Clear to Send (CTS)
signal shows the actual status of the command buffer of the radio. It can be monitored over the SPI or on GPIOs, or
the chip can generate an interrupt if it is ready to receive the next command. These three options are detailed
below.
Table 5. List of the Radio API Properties
Property
Group
Number Name Description Default
0x01 0x00 INT_CTL_ENABLE Interrupt enable property 0x04
0x01 0x01 INT_CTL_PH_ENABLE Packet handler interrupt enable property 0x00
0x01 0x02 INT_CTL_MODEM_ENABLE Modem interrupt enable property 0x00
0x01 0x03 INT_CTL_CHIP_ENABLE Chip interrupt enable property 0x04
0x02 0x00 FRR_CTL_A_MODE Fast Response Register A Configuration 0x01
0x02 0x01 FRR_CTL_B_MODE Fast Response Register B Configuration 0x02
0x02 0x02 FRR_CTL_C_MODE Fast Response Register C Configuration 0x09
0x02 0x03 FRR_CTL_D_MODE Fast Response Register D Configuration 0x00
0x22 0x01 PA_PWR_LVL PA Level Configuration 0x7F
0x24 0x03 EZCONFIG_XO_TUNE
Configure crystal oscillator frequency tuning
bank
0x40
0x40 0x00 FREQ_CONTROL_INTE Frac-N PLL integer number 0x3C
0x40 0x01 FREQ_CONTROL_FRAC_2 Byte 2 of Frac-N PLL fraction number 0x08
0x40 0x02 FREQ_CONTROL_FRAC_1 Byte 1 of Frac-N PLL fraction number 0x08
0x40 0x03 FREQ_CONTROL_FRAC_0 Byte 0 of Frac-N PLL fraction number 0x08
0x40 0x04
FREQ_CONTROL_CHANNEL_-
STEP_SIZE_1
Byte 1 of channel step size
0x00
0x40 0x05
FREQ_CONTROL_CHANNEL_-
STEP_SIZE_0
Byte 0 of channel step size
0x00