Silicon Laboratories Si3452MS8, User Manual

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S i 3 4 5 2 M S 8 - K I T
16 Rev. 0.6
7.2. Si3452 Schematics
VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6
+1V1REG
+1.24REG
+1V1REG
VOUT7
RST
SCL SDA
INT
SDA SCL
+3V3
-52V
+3V3
+3V3
-52V
-52V
+3V3
-52V
+3V3
+3V3LV
+3V3
+3V3
+3V3LV
+3V3LV
+3V3LV
PWR Status LED
+1V1 Reg
INPUT POWER
UNISOLATED
BULK DECOUPLING
Connect to EGND at Mount Holes
<50
Isolation bypass
PoE magnetics and LEDs
*Note: For most designs, the Si8405 isolator "A" side should face the system host. If the Si8405 isolator A side faces the Si3452, please use a 3k pull-up resistor for robust low-temperature operation.
See *Note
J4
HEADER 12x2
J4
HEADER 12x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R105 330 R105 330
C102 680pF C102 680pF
R100
10K
R100
10K
TPV3 TPV TPV3 TPV
+3V3
NI
+3V3
NI
C103 0.1uF C103 0.1uF
R106
267
R106
267
D101 GREEN
3.3V PWR
D101 GREEN
3.3V PWR
R107 267 R107 267
SW1
SW PUSHBUTTON
SW1
SW PUSHBUTTON
-52V
NI
-52V
NI
TP103 GND TP103 GND
TPV2 TPV TPV2 TPV
+
C104 33uF
+
C104 33uF
J104 HEADER 5x2 J104 HEADER 5x2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
TP104 GND TP104 GND
R104 44.2K R104 44.2K
R102 1K R102 1K
VREG
-52V->+3.3V Converter
+3V3
+3V3_RTN
-52V -52V_RTN
C100
1uF
C100
1uF
TP102 GND TP102 GND
R101 1K R101 1K
J100
CONN SOCKET 3x2 RA
J100
CONN SOCKET 3x2 RA
1
1
2
2
3
3
4
4
5
5
6
6
R108 2.1K R108 2.1K
C107 1uF C107 1uF
U100 TLV431 U100 TLV431
TPV4 TPV TPV4 TPV
R103 10K R103 10K
C101 680pF C101 680pF
ISOLATION
U101 Si8405
ISOLATION
U101 Si8405
VDD1
1
VDD2
16
GND2
9
GND1
8
NC
2
NC
15
A1
3
A2
4
B3
12
B4
11
A3
5
A4
6
B1
14
B2
13
NC
7
NC
10
TPV1 TPV TPV1 TPV
C106 10uF C106 10uF
D100 MBRS3100T3 D100 MBRS3100T3
J101 CONN TRBLK 2 J101 CONN TRBLK 2
1 2
C108 1uF C108 1uF
+
C105 33uF
+
C105 33uF
HV Port Controllers
+3V3
+3V3_RTN
-52V
VREF_IN RESET_L
VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT0
SDA SCL INT
-52V_RTN
Figure
1
9.
T
op Lev
el