Silicon Laboratories MGM13S Series Manual Download Page 93

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LOCATION

Functionality

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4 - 7

8 - 11

12 - 15

16 - 19

20 - 23

24 - 27

28 - 31

Description

LEU0_RX

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

6: PB12

7: PB13

8: PB14

9: PB15

10: PC6

11: PC7

12: PC8

13: PC9

14: PC10

15: PC11

16: PD9

17: PD10

18: PD11

19: PD12

20: PD13

21: PD14

22: PD15

23: PF0

24: PF1

25: PF2

26: PF3

27: PF4

28: PF5

29: PF6

30: PF7

31: PA0

LEUART0 Receive
input.

LEU0_TX

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

7: PB12

8: PB13

9: PB14

10: PB15

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

17: PD9

18: PD10

19: PD11

20: PD12

21: PD13

22: PD14

23: PD15

24: PF0

25: PF1

26: PF2

27: PF3

28: PF4

29: PF5

30: PF6

31: PF7

LEUART0 Transmit
output. Also used
as receive input in
half duplex commu-
nication.

LFXTAL_N

0: PB14

Low Frequency
Crystal (typically
32.768 kHz) nega-
tive pin. Also used
as an optional ex-
ternal clock input
pin.

LFXTAL_P

0: PB15

Low Frequency
Crystal (typically
32.768 kHz) posi-
tive pin.

MODEM_DCLK

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

7: PB12

8: PB13

9: PB14

10: PB15

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

17: PD9

18: PD10

19: PD11

20: PD12

21: PD13

22: PD14

23: PD15

24: PF0

25: PF1

26: PF2

27: PF3

28: PF4

29: PF5

30: PF6

31: PF7

MODEM data clock
out.

MODEM_DIN

0: PA1

1: PA2

2: PA3

3: PA4

4: PA5

5: PB11

6: PB12

7: PB13

8: PB14

9: PB15

10: PC6

11: PC7

12: PC8

13: PC9

14: PC10

15: PC11

16: PD9

17: PD10

18: PD11

19: PD12

20: PD13

21: PD14

22: PD15

23: PF0

24: PF1

25: PF2

26: PF3

27: PF4

28: PF5

29: PF6

30: PF7

31: PA0

MODEM data in.

MODEM_DOUT

0: PA2

1: PA3

2: PA4

3: PA5

4: PB11

5: PB12

6: PB13

7: PB14

8: PB15

9: PC6

10: PC7

11: PC8

12: PC9

13: PC10

14: PC11

15: PD9

16: PD10

17: PD11

18: PD12

19: PD13

20: PD14

21: PD15

22: PF0

23: PF1

24: PF2

25: PF3

26: PF4

27: PF5

28: PF6

29: PF7

30: PA0

31: PA1

MODEM data out.

OPA0_N

0: PA4

Operational Amplifi-
er 0 external nega-
tive input.

OPA0_P

0: PA2

Operational Amplifi-
er 0 external posi-
tive input.

OPA1_N

0: PD15

Operational Amplifi-
er 1 external nega-
tive input.

OPA1_P

0: PD13

Operational Amplifi-
er 1 external posi-
tive input.

MGM13S Mighty Gecko SiP Module Data Sheet

Pin Definitions

silabs.com

| Building a more connected world.

Rev. 1.0 | 93

Summary of Contents for MGM13S Series

Page 1: ... operational USART Low Energy UARTTM I2 C External Interrupts General Purpose I O Pin Reset Pin Wakeup ADC VDAC Analog Comparator EM3 Stop EM2 Deep Sleep EM1 Sleep EM4 Hibernate EM4 Shutoff EM0 Active Energy Management Brown Out Detector DC DC Converter Voltage Regulator Voltage Monitor Power On Reset Other Capacitive Touch Op Amp IDAC CRYPTO CRC True Random Number Generator SMU Core Memory ARM Co...

Page 2: ...模式保留 16 kB RAM RTCC 从 LFRCO 中运行下电流为 1 3 μA 无线模块唤醒带有信号强度检测前导模式检测帧检测和超时监管认证 FCC CE IC ISEDC MIC Telec 运行范围宽 1 8 V 至 3 8 V 单电源 40 C 至 85 C 尺寸 6 5 mm 6 5 mm 1 4 mm 互联网安全支持通用 CRC 真随机数生成器 TRNG 2 倍硬件加密加速支持 AES 128 256 SHA 1 SHA 2 SHA 224 和 SHA 256 以及 ECC 广泛的 MCU 外围设备选择 12 位 1 Msps SAR 模拟数字转换器 ADC 2 个模拟比较器 ACMP 2 个数字模拟电压转换器 VDAC 3 个运算放大器 Opamp 数字模拟电流转换器 IDAC 低功耗传感器接口 LESENSE 多通道电容式感应接口 CSEN 32 个...

Page 3: ... MGM13S02F512GA V2 Bluetooth LE Zigbee Thread 10 dBm Built in 512 64 32 Cut Tape MGM13S02F512GA V2R Bluetooth LE Zigbee Thread 10 dBm Built in 512 64 32 Reel MGM13S02F512GN V2 Bluetooth LE Zigbee Thread 10 dBm RF pin 512 64 32 Cut Tape MGM13S02F512GN V2R Bluetooth LE Zigbee Thread 10 dBm RF pin 512 64 32 Reel End product manufacturers must verify that the module is configured to meet regulatory li...

Page 4: ... up Timer CRYOTIMER 11 3 6 6 Pulse Counter PCNT 12 3 6 7 Watchdog Timer WDOG 12 3 7 Communications and Other Digital Peripherals 12 3 7 1 Universal Synchronous Asynchronous Receiver Transmitter USART 12 3 7 2 Low Energy Universal Asynchronous Receiver Transmitter LEUART 12 3 7 3 Inter Integrated Circuit Interface I2C 12 3 7 4 Peripheral Reflex System PRS 12 3 7 5 Low Energy Sensor Interface LESENS...

Page 5: ...s 30 4 1 9 Oscillators 41 4 1 10 Flash Memory Characteristics 44 4 1 11 General Purpose I O GPIO 45 4 1 12 Voltage Monitor VMON 46 4 1 13 Analog to Digital Converter ADC 47 4 1 14 Analog Comparator ACMP 49 4 1 15 Digital to Analog Converter VDAC 52 4 1 16 Current Digital to Analog Converter IDAC 55 4 1 17 Capacitive Sense CSEN 57 4 1 18 Operational Amplifier OPAMP 59 4 1 19 Pulse Counter PCNT 62 4...

Page 6: ...ensions 110 8 2 MGM13S Recommeded PCB Land Pattern 113 8 3 MGM13S Package Marking 117 9 Soldering Recommendations 118 9 1 Soldering Recommendations 118 10 Certifications 119 10 1 Qualified Antenna Types 119 10 2 Bluetooth 119 10 3 CE 119 10 4 FCC 120 10 5 ISED Canada 121 10 6 Japan 123 11 Revision History 124 silabs com Building a more connected world Rev 1 0 6 ...

Page 7: ...vers PFn Port D Drivers PDn Port C Drivers PCn Port B Drivers PBn Port A Drivers PAn Mux FB DC DC Converter Debug Signals shared w GPIO Brown Out Power On Reset Reset Management Unit Serial Wire and ETM Debug Programming AUXHFRCO Radio Transciever RF Frontend PA I Q LNA BALUN Frequency Synthesizer DEMOD AGC IFADC CRC BUFC MOD FRC RAC PGA Antenna Chip Antenna Matching 1V8 Voltage Regulator Voltage ...

Page 8: ...roller has a packet and state trace unit that provides valuable information during the development phase It features Non intrusive trace of transmit data receive data and state information Data observability on a single pin UART data output or on a two pin SPI data output Configurable data output bitrate baudrate Multiplexed transmitted data received data and state meta information in a single ser...

Page 9: ...xternal and internal supplies of the module are connected for different part numbers MGM13S02 Module I O Interfaces IOVDD 1V8 DC DC IOVDD DVDD RFVDD VBATT Digital RF VREGVDD 220nF 4 9µF EFR32MG13 SoC 10nF 4 7µF VREGSW 4 7µH PAVDD RF PA Analog 2 2µF DECOUPLE AVDD Figure 3 2 Power Supply Configuration for MGM13S02xxx Devices MGM13S12 Module I O Interfaces IOVDD 1V8 DC DC IOVDD DVDD RFVDD VBATT Digit...

Page 10: ...eration in EM2 and EM3 If all of the peripherals in a peripheral power domain are configured as unused the power domain for that group will be powered off in the low power mode reducing the overall current consumption of the device Table 3 2 Peripheral Power Subdomains Peripheral Power Domain 1 Peripheral Power Domain 2 ACMP0 ACMP1 PCNT0 CSEN ADC0 VDAC0 LETIMER0 LEUART0 LESENSE I2C0 APORT I2C1 IDA...

Page 11: ...modes In capture mode the counter state is stored in a buffer at a selected input event In compare mode the channel output reflects the comparison of the counter to a programmed thresh old value In PWM mode the WTIMER supports generation of pulse width modulation PWM outputs of arbitrary waveforms defined by the sequence of values written to the compare registers with optional dead time insertion ...

Page 12: ...on rates from 10 kbit s up to 1 Mbit s Slave arbitration and timeouts are also available allowing implementation of an SMBus compliant system The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated transfers Automatic recognition of slave addresses is provided in active and low energy modes 3 7 4 Peripheral Reflex Syst...

Page 13: ...ents can operate differentially buses are grouped by X Y pairs 3 9 2 Analog Comparator ACMP The Analog Comparator is used to compare the voltage of two analog inputs with a digital output indicating which input voltage is high er Inputs are selected from among internal references and external pins The tradeoff between response time and current consumption is configurable by software Two 6 bit refe...

Page 14: ...opamps save energy PCB space and cost as compared with standalone opamps because they are integrated on chip 3 10 Reset Management Unit RMU The RMU is responsible for handling reset of the MGM13S A wide range of reset sources are available including several power supply monitors pin reset software controlled reset core lockup reset and watchdog reset 3 11 Core and Memory 3 11 1 Processor Core The ...

Page 15: ...the figures below RAM and flash sizes are for the largest memory configuration Figure 3 4 MGM13S Memory Map Core Peripherals and Code Space MGM13S Mighty Gecko SiP Module Data Sheet System Overview silabs com Building a more connected world Rev 1 0 15 ...

Page 16: ... periph eral instances All remaining peripherals support full configuration Table 3 3 Configuration Summary Peripheral Configuration Pin Connections USART0 IrDA SmartCard US0_TX US0_RX US0_CLK US0_CS USART1 IrDA I2S SmartCard US1_TX US1_RX US1_CLK US1_CS USART2 IrDA SmartCard US2_TX US2_RX US2_CLK US2_CS TIMER0 with DTI TIM0_CC 2 0 TIM0_CDTI 2 0 TIMER1 TIM1_CC 3 0 WTIMER0 with DTI WTIM0_CC 2 0 WTI...

Page 17: ...m values represent the worst conditions across supply voltage process variation and operating temperature unless stated otherwise The MGM13S module is powered primarily from the VBATT supply pin GPIO are powered from the IOVDD supply pin There are also several internal supply rails mentioned in the electrical specifications whose connections vary based on transmit power configuration Refer to 3 3 ...

Page 18: ... of 5 25 and IOVDD 2 V Standard GPIO pins 0 3 IOVDD 0 3 V Maximum RF level at input PRFMAX2G4 10 dBm Total current into supply pins IVDDMAX Source 200 mA Total current into VSS ground lines IVSSMAX Sink 200 mA Current per I O pin IIOMAX Sink 50 mA Source 50 mA Current for all I O pins IIOALLMAX Sink 200 mA Source 200 mA Junction temperature TJ 40 105 C Note 1 When a GPIO pin is routed to the analo...

Page 19: ...gulation 2 4 3 3 3 8 V DCDC in bypass 50mA load 1 8 3 3 3 8 V VBATT current IVBATT DCDC in bypass T 85 C 200 mA HFCORECLK frequency fCORE VSCALE2 MODE WS1 40 MHz VSCALE0 MODE WS0 20 MHz HFCLK frequency fHFCLK VSCALE2 40 MHz VSCALE0 20 MHz Note 1 The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table Requirements for other loads can be calculated as V...

Page 20: ...ow Power LP mode LPCMPBIASEMxx3 3 1 8 V tar get output IDCDC_LOAD 10 mA 1 63 2 1 V Steady state output ripple VR Radio disabled 3 mVpp Output voltage under over shoot VOV CCM Mode LNFORCECCM3 1 Load changes between 0 mA and 100 mA 25 60 mV DCM Mode LNFORCECCM3 0 Load changes between 0 mA and 10 mA 45 90 mV Overshoot during LP to LN CCM DCM mode transitions com pared to DC level in LN mode 200 mV U...

Page 21: ...controller is a hysteretic controller that maintains the output voltage within the specified limits 3 LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the EMU_DCDCLOEM01CFG register depending on the energy mode 4 Drive levels are defined by configuration of the PFETCNT and NFETCNT registers Light Drive PFETCNT NFETCNT 3 Medi um Drive PFETCNT NFETC...

Page 22: ... IACTIVE_CCM 38 4 MHz crystal CPU running while loop from flash2 97 µA MHz 38 MHz HFRCO CPU running Prime from flash 80 µA MHz 38 MHz HFRCO CPU running while loop from flash 81 µA MHz 38 MHz HFRCO CPU running CoreMark from flash 92 µA MHz 26 MHz HFRCO CPU running while loop from flash 94 µA MHz 1 MHz HFRCO CPU running while loop from flash 1145 µA MHz Current consumption in EM0 mode with all perip...

Page 23: ...VS 128 byte RAM retention RTCC running from LFXO 0 75 µA 128 byte RAM retention CRYO TIMER running from ULFRCO 0 44 µA 128 byte RAM retention no RTCC 0 42 µA Current consumption in EM4S mode IEM4S No RAM retention no RTCC 0 07 µA Note 1 DCDC Low Noise DCM Mode Light Drive PFETCNT NFETCNT 3 F 3 0 MHz RCOBAND 0 ANASW DVDD 2 CMU_HFXOCTRL_LOWPOWER 0 3 DCDC Low Noise CCM Mode Light Drive PFETCNT NFETCN...

Page 24: ...ng while loop from flash 206 µA MHz Current consumption in EM1 mode with all peripherals dis abled IEM1 38 4 MHz crystal1 76 µA MHz 38 MHz HFRCO 47 µA MHz 26 MHz HFRCO 48 µA MHz 1 MHz HFRCO 191 µA MHz Current consumption in EM1 mode with all peripherals dis abled and voltage scaling enabled IEM1_VS 19 MHz HFRCO 43 µA MHz 1 MHz HFRCO 163 µA MHz Current consumption in EM2 mode with voltage scaling e...

Page 25: ...ition Min Typ Max Unit Note 1 CMU_HFXOCTRL_LOWPOWER 0 2 CMU_LFRCOCTRL_ENVREF 1 CMU_LFRCOCTRL_VREFUPDATE 1 MGM13S Mighty Gecko SiP Module Data Sheet Electrical Specifications silabs com Building a more connected world Rev 1 0 25 ...

Page 26: ... loop from flash 209 µA MHz Current consumption in EM1 mode with all peripherals dis abled IEM1 38 4 MHz crystal1 76 µA MHz 38 MHz HFRCO 47 51 µA MHz 26 MHz HFRCO 49 55 µA MHz 1 MHz HFRCO 195 374 µA MHz Current consumption in EM1 mode with all peripherals dis abled and voltage scaling enabled IEM1_VS 19 MHz HFRCO 43 µA MHz 1 MHz HFRCO 167 µA MHz Current consumption in EM2 mode with voltage scaling...

Page 27: ...k prescaled by 4 10 5 mA 802 15 4 receiving frame F 2 4 GHz Radio clock prescaled by 3 10 4 mA Current consumption in re ceive mode listening for packet MCU in EM1 38 4 MHz peripheral clocks disa bled T 85 C IRX_LISTEN 125 kbit s 2GFSK F 2 4 GHz No radio clock prescaling 10 4 mA 500 kbit s 2GFSK F 2 4 GHz No radio clock prescaling 10 4 mA 1 Mbit s 2GFSK F 2 4 GHz No radio clock prescaling 10 7 mA ...

Page 28: ...2 requires approximately 30 3 µs 28 HFCLKs 3 VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV µs for approximately 20 µs During this transition peak currents will be dependent on the value of the DECOUPLE output capacitor from 35 mA with a 1 µF capacitor to 70 mA with a 2 7 µF capacitor 4 Scaling down from VSCALE2 to VSCALE0 requires approximately 2 8 µs 29 HFCLKs 4 1 6 Brown...

Page 29: ...3 5 MHz LO tuning frequency resolu tion with 38 4 MHz crystal fRES 2400 2483 5 MHz 73 Hz Frequency deviation resolu tion with 38 4 MHz crystal dfRES 2400 2483 5 MHz 73 Hz Maximum frequency devia tion with 38 4 MHz crystal dfMAX 2400 2483 5 MHz 1677 kHz MGM13S Mighty Gecko SiP Module Data Sheet Electrical Specifications silabs com Building a more connected world Rev 1 0 29 ...

Page 30: ...D connected directly to ex ternal supply for output power 10 dBm 4 5 dB 1 8 V VVREGVDD 3 3 V PAVDD connected directly to ex ternal supply for output power 10 dBm 3 6 dB 1 8 V VVREGVDD 3 3 V using DC DC converter 2 1 dB Output power variation vs temperature at POUTMAX POUTVAR_T From 40 to 85 C PAVDD con nected to DC DC output 1 7 dB From 40 to 85 C PAVDD con nected to external supply 1 7 dB Output ...

Page 31: ...ous emission SPURRX 30 MHz to 1 GHz 57 dBm 1 GHz to 12 GHz 47 dBm Max spurious emissions dur ing active receive mode per FCC Part 15 109 a SPURRX_FCC 216 MHz to 960 MHz Conducted Measurement 55 2 dBm Above 960 MHz Conducted Measurement 47 2 dBm Level above which RFSENSE will trigger1 RFSENSETRIG CW at 2 45 GHz 24 dBm Level below which RFSENSE will not trigger1 RFSENSETHRES CW at 2 45 GHz 50 dBm No...

Page 32: ...eference sensitivity level2 ACRM1 Interferer is reference signal at 1 channel spacing 40 7 dB Interferer is filtered reference sig nal3 at 1 channel spacing 49 3 dB Interferer is CW at 1 channel spacing 57 9 dB Alternate channel rejection 1 PER Desired is refer ence signal at 3dB above reference sensitivity level2 ACR2 Interferer is reference signal at 2 channel spacing 52 0 dB Interferer is filte...

Page 33: ...as defined by the IEEE 802 11 specification and IEEE 802 11g adden dum 4 1 8 4 RF Transmitter Characteristics for Bluetooth Low Energy in the 2 4GHz Band 125 kbps Data Rate Unless otherwise indicated typical conditions are T 25 C VBATT 3 3 V DC DC on Crystal frequency 38 4 MHz RF center frequency 2 45 GHz Conducted measurement from the antenna feedpoint Table 4 14 RF Transmitter Characteristics fo...

Page 34: ...d is reference signal at 79 dBm C I1 Interferer is reference signal at 1 MHz offset Desired frequency 2402 MHz Fc 2480 MHz 14 0 dB N 1 adjacent channel selec tivity 0 1 BER with allowa ble exceptions Desired is reference signal at 79 dBm C I1 Interferer is reference signal at 1 MHz offset Desired frequency 2402 MHz Fc 2480 MHz 13 6 dB Selectivity to image frequen cy 0 1 BER Desired is ref erence s...

Page 35: ... 247 at 10 dBm 9 8 dBm 3kHz Per FCC part 15 247 at 20 dBm1 8 dBm 3kHz Spurious emissions out of band excluding harmonics captured in SPURHARM FCC Emissions taken at POUTMAX PAVDD connec ted to external 3 3 V supply SPUROOB_FCC Per FCC part 15 205 15 209 Above 2 483 GHz or below 2 4 GHz continuous transmission of CW carrier Restricted Bands2 3 47 dBm Note 1 Output power limited to 14 dBm to ensure ...

Page 36: ...ency 2402 MHz Fc 2480 MHz 9 2 dB N 1 adjacent channel selec tivity 0 1 BER with allowa ble exceptions Desired is reference signal at 72 dBm C I1 Interferer is reference signal at 1 MHz offset Desired frequency 2402 MHz Fc 2480 MHz 9 0 dB Alternate selectivity 0 1 BER with allowable excep tions Desired is reference signal at 72 dBm C I2 Interferer is reference signal at 2 MHz offset Desired frequen...

Page 37: ... dBm Spurious emissions out of band excluding harmonics captured in SPURHARM FCC Emissions taken at POUTMAX PAVDD connec ted to external 3 3 V supply SPUROOB_FCC Per FCC part 15 205 15 209 Above 2 483 GHz or below 2 4 GHz continuous transmission of CW carrier Restricted Bands2 3 47 dBm Note 1 Per Bluetooth Core_5 0 Vol 6 Part A Section 3 2 2 exceptions are allowed in up to three bands of 1 MHz wid...

Page 38: ... exceptions Desired is reference signal at 67 dBm C I1 Interferer is reference signal at 1 MHz offset Desired frequency 2402 MHz Fc 2480 MHz 1 6 dB Alternate selectivity 0 1 BER with allowable excep tions Desired is reference signal at 67 dBm C I2 Interferer is reference signal at 2 MHz offset Desired frequency 2402 MHz Fc 2480 MHz 42 0 dB Alternate selectivity 0 1 BER with allowable excep tions D...

Page 39: ...SPURHARM FCC Emissions taken at POUTMAX PAVDD connec ted to external 3 3 V supply SPUROOB_FCC Per FCC part 15 205 15 209 Above 2 483 GHz or below 2 4 GHz continuous transmission of CW carrier Restricted Bands2 3 4 5 47 dBm Note 1 Per Bluetooth Core_5 0 Vol 6 Part A Section 3 2 2 exceptions are allowed in up to three bands of 1 MHz width centered on a frequency which is an integer multiple of 1 MHz...

Page 40: ... exceptions Desired is reference signal at 67 dBm C I1 Interferer is reference signal at 2 MHz offset Desired frequency 2402 MHz Fc 2480 MHz 11 4 dB Alternate selectivity 0 1 BER with allowable excep tions Desired is reference signal at 67 dBm C I2 Interferer is reference signal at 4 MHz offset Desired frequency 2402 MHz Fc 2480 MHz 40 3 dB Alternate selectivity 0 1 BER with allowable excep tions ...

Page 41: ...hm CL 7 pF GAIN4 2 308 ms Note 1 Total load capacitance as seen by the crystal 2 The effective load capacitance seen by the crystal will be CLFXO_T 2 This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal 3 Block is supplied by AVDD if ANASW 0 or DVDD if ANASW 1 in EMU_PWRCTRL register 4 In CMU_LFXOCTRL register 4 1 9 2 High Frequency Crystal Oscillat...

Page 42: ...kHz ENVREF1 0 31 3 32 768 33 4 kHz Startup time tLFRCO 500 µs Current consumption 2 ILFRCO ENVREF 1 in CMU_LFRCOCTRL 342 nA ENVREF 0 in CMU_LFRCOCTRL 494 nA Note 1 In CMU_LFRCOCTRL register 2 Block is supplied by AVDD if ANASW 0 or DVDD if ANASW 1 in EMU_PWRCTRL register MGM13S Mighty Gecko SiP Module Data Sheet Electrical Specifications silabs com Building a more connected world Rev 1 0 42 ...

Page 43: ...18 135 µA fHFRCO 7 MHz 89 100 µA fHFRCO 4 MHz 34 44 µA fHFRCO 2 MHz 29 40 µA fHFRCO 1 MHz 26 36 µA Coarse trim step size of period SSHFRCO_COARS E 0 8 Fine trim step size of pe riod SSHFRCO_FINE 0 1 Period jitter PJHFRCO 0 2 RMS Frequency limits fHFRCO_BAND FREQRANGE 0 FINETUNIN GEN 0 3 47 6 15 MHz FREQRANGE 3 FINETUNIN GEN 0 6 24 11 45 MHz FREQRANGE 6 FINETUNIN GEN 0 11 3 19 8 MHz FREQRANGE 7 FIN...

Page 44: ...e Erase 2 0 mA Write current6 IWRITE 3 5 mA Supply voltage during flash erase and write VFLASH 1 62 3 6 V Note 1 Flash data retention information is published in the Quarterly Quality and Reliability Report 2 From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0 Internal setup and hold times for flash control signals are included 3 Mass erase is issue...

Page 45: ...tive to IOVDD VOL Sinking 3 mA IOVDD 3 V DRIVESTRENGTH1 WEAK IOVDD 0 2 V Sinking 1 2 mA IOVDD 1 62 V DRIVESTRENGTH1 WEAK IOVDD 0 4 V Sinking 20 mA IOVDD 3 V DRIVESTRENGTH1 STRONG IOVDD 0 2 V Sinking 8 mA IOVDD 1 62 V DRIVESTRENGTH1 STRONG IOVDD 0 4 V Input leakage current IIOLEAK All GPIO except LFXO pins GPIO IOVDD 0 1 30 nA LFXO Pins GPIO IOVDD 0 1 50 nA Input leakage current on 5VTOL pads above...

Page 46: ...ON In EM0 or EM1 1 active channel 6 3 8 µA In EM0 or EM1 All channels ac tive 12 5 15 µA In EM2 EM3 or EM4 1 channel active and above threshold 62 nA In EM2 EM3 or EM4 1 channel active and below threshold 62 nA In EM2 EM3 or EM4 All channels active and above threshold 99 nA In EM2 EM3 or EM4 All channels active and below threshold 99 nA Loading of monitored supply ISENSE In EM0 or EM1 2 µA In EM2 ...

Page 47: ...0 GPBIASACC 1 4 8 µA Current from all supplies us ing internal reference buffer Duty cycled operation AWARMUPMODE3 KEEP INSTANDBY or KEEPIN SLOWACC IADC_STAND BY_LP 125 ksps 16 MHz ADCCLK BIA SPROG 0 GPBIASACC 1 4 105 µA 35 ksps 16 MHz ADCCLK BIA SPROG 0 GPBIASACC 1 4 70 µA Current from all supplies us ing internal reference buffer Continuous operation WAR MUPMODE3 KEEPADC WARM IADC_CONTINU OUS_HP...

Page 48: ... the power rail supplied to on chip circuitry and may be lower than the effective full scale voltage All ADC inputs are limited to the ADC supply AVDD or DVDD depending on EMU_PWRCTRL_ANASW Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin 2 PSRR is referenced to AVDD when ANASW 0 and to DVDD when ANASW 1 in EMU_PWRCTRL 3 In ADCn_CNTL register 4 In ADCn_...

Page 49: ...voltage reference3 IACMP BIASPROG2 1 FULLBIAS2 0 50 nA BIASPROG2 0x10 FULLBIAS2 0 306 nA BIASPROG2 0x02 FULLBIAS2 1 6 1 11 µA BIASPROG2 0x20 FULLBIAS2 1 74 92 µA Current consumption of inter nal voltage reference3 IACMPREF VLP selected as input using 2 5 V Reference 4 0 625 V 50 nA VLP selected as input using VDD 20 nA VBDIV selected as input using 1 25 V reference 1 4 1 µA VADIV selected as input...

Page 50: ... 130 78 30 mV HYSTSEL4 HYST15 155 88 34 mV Comparator delay5 tACMPDELAY BIASPROG2 1 FULLBIAS2 0 30 95 µs BIASPROG2 0x10 FULLBIAS2 0 3 7 10 µs BIASPROG2 0x02 FULLBIAS2 1 360 1000 ns BIASPROG2 0x20 FULLBIAS2 1 35 ns Offset voltage VACMPOFFSET BIASPROG2 0x10 FULLBIAS2 1 35 35 mV Reference voltage VACMPREF Internal 1 25 V reference 1 1 25 1 47 V Internal 2 5 V reference 1 98 2 5 2 8 V Capacitive sense...

Page 51: ...Pn_CTRL register 3 The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference IACMPTOTAL IACMP IACMPREF 4 In ACMPn_HYSTERESIS registers 5 100 mV differential drive 6 In ACMPn_INPUTSEL register MGM13S Mighty Gecko SiP Module Data Sheet Electrical Specifications silabs com Building a more connected world Rev 1 0 51 ...

Page 52: ...rom HFPERCLK3 IDAC_CLK 5 8 µA MHz Sample rate SRDAC 500 ksps DAC clock frequency fDAC 1 MHz Conversion time tDACCONV fDAC 1MHz 2 µs Settling time tDACSETTLE 50 fs step settling to 5 LSB 2 5 µs Startup time tDACSTARTUP Enable to 90 fs output settling to 10 LSB 12 µs Output impedance ROUT DRIVESTRENGTH 2 0 4 V VOUT VOPA 0 4 V 8 mA IOUT 8 mA Full supply range 2 Ω DRIVESTRENGTH 0 or 1 0 4 V VOUT VOPA ...

Page 53: ...differential internal 1 25V reference 67 8 dB 500 ksps differential internal 2 5V reference 69 0 dB 500 ksps differential 3 3V VDD reference 68 5 dB Total harmonic distortion THD 70 2 dB Differential non linearity5 DNLDAC 0 99 1 LSB Intergral non linearity INLDAC 4 4 LSB Offset error6 VOFFSET T 25 C 8 8 mV Across operating temperature range 25 25 mV Gain error6 VGAIN T 25 C Low noise internal ref ...

Page 54: ...t from HFPERCLK is dependent on HFPERCLK frequency This current contributes to the total supply current used when the clock to the DAC module is enabled in the CMU 4 PSRR calculated as 20 log10 ΔVDD ΔVOUT VDAC output at 90 of full scale 5 Entire range is monotonic and has no missing codes 6 Gain is calculated by measuring the slope from 10 to 90 of full scale Offset is calculated by comparing actu...

Page 55: ...V T 25 C 3 3 EM0 or EM1 Across operating temperature range 18 22 EM2 or EM3 Source mode RANGSEL1 RANGE0 AVDD 3 3 V T 25 C 2 EM2 or EM3 Source mode RANGSEL1 RANGE1 AVDD 3 3 V T 25 C 1 7 EM2 or EM3 Source mode RANGSEL1 RANGE2 AVDD 3 3 V T 25 C 0 8 EM2 or EM3 Source mode RANGSEL1 RANGE3 AVDD 3 3 V T 25 C 0 5 EM2 or EM3 Sink mode RANG SEL1 RANGE0 AVDD 3 3 V T 25 C 0 7 EM2 or EM3 Sink mode RANG SEL1 RA...

Page 56: ...rent sourced at 0 V ICOMP_SRC RANGESEL1 0 output voltage min VIOVDD VAVDD 2 100 mV 0 11 RANGESEL1 1 output voltage min VIOVDD VAVDD 2 100 mV 0 06 RANGESEL1 2 output voltage min VIOVDD VAVDD 2 150 mV 0 04 RANGESEL1 3 output voltage min VIOVDD VAVDD 2 250 mV 0 03 Output voltage compliance in sink mode sink current change relative to current sunk at IOVDD ICOMP_SINK RANGESEL1 0 output voltage 100 mV ...

Page 57: ...n 1x 10 chan nels bonded total capacitance of 330 pF 1 226 nA 12 bit SAR conversions 200 ms conversion rate IREFPROG 7 Gain 1x 10 channels bonded total capacitance of 330 pF 1 33 nA Delta Modulation conversions 200 ms conversion rate IRE FPROG 7 Gain 1x 10 chan nels bonded total capacitance of 330 pF 1 25 nA Supply current EM2 scan conversions WARMUP MODE NORMAL WAR MUPCNT 0 ICSEN_EM2 12 bit SAR c...

Page 58: ...rent is specified with a total external capacitance of 33 pF per channel Average current is dependent on how long the module is actively sampling channels within the scan period and scales with the number of samples acquired Supply current for a specif ic application can be estimated by multiplying the current per sample by the total number of samples per period total_current single_sample_current...

Page 59: ...pF OUTSCALE 1 37 5 pF Output impedance ROUT DRIVESTRENGTH 2 or 3 0 4 V VOUT VOPA 0 4 V 8 mA IOUT 8 mA Buffer connection Full supply range 0 25 Ω DRIVESTRENGTH 0 or 1 0 4 V VOUT VOPA 0 4 V 400 µA IOUT 400 µA Buffer connection Full supply range 0 6 Ω DRIVESTRENGTH 2 or 3 0 1 V VOUT VOPA 0 1 V 2 mA IOUT 2 mA Buffer connection Full supply range 0 4 Ω DRIVESTRENGTH 0 or 1 0 1 V VOUT VOPA 0 1 V 100 µA I...

Page 60: ...RIVESTRENGTH 3 Buffer connection 67 DRIVESTRENGTH 2 Buffer connection 69 DRIVESTRENGTH 1 Buffer connection 63 DRIVESTRENGTH 0 Buffer connection 68 Output voltage noise NOUT DRIVESTRENGTH 3 Buffer connection 10 Hz 10 MHz 146 µVrms DRIVESTRENGTH 2 Buffer connection 10 Hz 10 MHz 163 µVrms DRIVESTRENGTH 1 Buffer connection 10 Hz 1 MHz 170 µVrms DRIVESTRENGTH 0 Buffer connection 10 Hz 1 MHz 176 µVrms D...

Page 61: ...STRENGTH 2 or 3 T 25 C 2 2 mV DRIVESTRENGTH 1 or 0 T 25 C 2 2 mV DRIVESTRENGTH 2 or 3 across operating temperature range 12 12 mV DRIVESTRENGTH 1 or 0 across operating temperature range 30 30 mV DC power supply rejection ratio9 PSRRDC Input referred 70 dB DC common mode rejection ratio9 CMRRDC Input referred 70 dB Total harmonic distortion THDOPA DRIVESTRENGTH 2 3x Gain connection 1 kHz VOUT 0 1 V...

Page 62: ... 8 From enable to output settled In sample and off mode RC network after OPAMP will contribute extra delay Settling error 1mV 9 When HCMDIS 1 and input common mode transitions the region from VOPA 1 4V to VOPA 1V input offset will change PSRR and CMRR specifications do not apply to this transition region 4 1 19 Pulse Counter PCNT Table 4 36 Pulse Counter PCNT Parameter Symbol Test Condition Min Ty...

Page 63: ...peated START condition hold time tHD_STA 4 µs STOP condition set up time tSU_STO 4 µs Bus free time between a STOP and START condition tBUF 4 7 µs Note 1 For CLHR set to 0 in the I2Cn_CTRL register 2 For the minimum HFPERCLK frequency required in Standard mode refer to the I2C chapter in the reference manual 3 The maximum SDA hold time tHD_DAT needs to be met only when the device does not stretch ...

Page 64: ...ART condition hold time tHD_STA 0 6 µs STOP condition set up time tSU_STO 0 6 µs Bus free time between a STOP and START condition tBUF 1 3 µs Note 1 For CLHR set to 1 in the I2Cn_CTRL register 2 For the minimum HFPERCLK frequency required in Fast mode refer to the I2C chapter in the reference manual 3 The maximum SDA hold time tHD DAT needs to be met only when the device does not stretch the low t...

Page 65: ...START condition set up time tSU_STA 0 26 µs Repeated START condition hold time tHD_STA 0 26 µs STOP condition set up time tSU_STO 0 26 µs Bus free time between a STOP and START condition tBUF 0 5 µs Note 1 For CLHR set to 0 or 1 in the I2Cn_CTRL register 2 For the minimum HFPERCLK frequency required in Fast mode Plus refer to the I2C chapter in the reference manual MGM13S Mighty Gecko SiP Module D...

Page 66: ... 42 ns MISO hold time 1 2 tH_MI 9 ns Note 1 Applies for both CLKPHA 0 and CLKPHA 1 figure only shows CLKPHA 0 2 Measurement done with 8 pF output loading at 10 and 90 of VDD figure shows 50 of VDD 3 tHFPERCLK is one period of the selected HFPERCLK CS SCLK CLKPOL 0 MOSI MISO tCS_MO tH_MI tSU_MI tSCKL_MO tSCLK SCLK CLKPOL 1 Figure 4 1 SPI Master Timing Diagram MGM13S Mighty Gecko SiP Module Data She...

Page 67: ...1 2 3 tH_MO 13 ns SCLK to MISO 1 2 3 tSCLK_MI 6 1 5 tHFPERCLK 45 2 5 tHFPERCLK ns Note 1 Applies for both CLKPHA 0 and CLKPHA 1 figure only shows CLKPHA 0 2 Measurement done with 8 pF output loading at 10 and 90 of VDD figure shows 50 of VDD 3 tHFPERCLK is one period of the selected HFPERCLK CS SCLK CLKPOL 0 MOSI MISO tCS_ACT_MI tSCLK_HI tSCLK tSU_MO tH_MO tSCLK_MI tCS_DIS_MI tSCLK_LO SCLK CLKPOL ...

Page 68: ...eet 500 ppm Bluetooth Sleep Clock accuracy requirement More accurate crystals can be used to reduce the listening window and thereby reduce overall current consumption Recommended crystal is KDS part number 1TJG125DP1A0012 or equivalent Note It is recommended to connect the RESETn line to the host CPU when NCP mode is used Wireless Module Host CPU RESETn PA0 UART_TX PA1 UART_RX PA2 UART_CTS PA3 UA...

Page 69: ...V8 However the 1V8 output is off by default and IOVDD must be powered when programming the device Any system that powers IOVDD directly from 1V8 must power IOVDD exter nally during initial programming Two common debug interface options are shown in Figure 5 3 Common Debug Connections on page 69 Refer to AN958 for more information and additional options PTI_FRAME PB13 PTI_DATA PB12 TCK SWCLK PF0 TM...

Page 70: ...n the antenna clearance area Connect all ground pads directly to a solid ground plane Place the ground vias as close to the ground pads as possible Figure 6 1 MGM13S PCB Top Layer Design The following rules are recommended for the PCB design Trace to copper clearance 150um PTH drill size 300um PTH annular ring 150um Important The antenna area must align with the pads precisely Please refer to the ...

Page 71: ... the PCB 6 2 Effect of PCB Width The MGM13S module should be placed at the center of the PCB edge The width of the board has an impact to the radiated efficiency and more importantly there should be enough ground plane on both sides of the module for optimal antenna performance Figure 6 4 MGM13S PCB Top Layer Design on page 71 gives an indcation of ground plane size vs maximum achievable range Fig...

Page 72: ... the module inside metal casing will prevent the radiation of the antenna Figure 6 5 Antenna Tuning on page 72 shows how it is possible to adjust the frequency of the antenna by adjusting the width of the antenna loop The antenna is extremely robust against any objects in close proximity or in direct contact with the antenna and it is rec ommended not to adjust the dimensions of the antenna area u...

Page 73: ...rn Plots Figure 6 6 Typical 2D Radiation Pattern Front View Figure 6 7 Typical 2D Radiation Pattern Side View MGM13S Mighty Gecko SiP Module Data Sheet Layout Guidelines silabs com Building a more connected world Rev 1 0 73 ...

Page 74: ...Figure 6 8 Typical 2D Radiation Pattern Top View MGM13S Mighty Gecko SiP Module Data Sheet Layout Guidelines silabs com Building a more connected world Rev 1 0 74 ...

Page 75: ...in connections and general descriptions of pin functionality For detailed information on the sup ported features for each GPIO pin see 7 2 GPIO Functionality Table or 7 3 Alternate Functionality Overview MGM13S Mighty Gecko SiP Module Data Sheet Pin Definitions silabs com Building a more connected world Rev 1 0 75 ...

Page 76: ...on verter Internally decoupled do not add external decoupling IOVDD 24 Digital IO power supply NC 25 No Connect PC6 26 GPIO 5V PC7 27 GPIO 5V PC8 28 GPIO 5V PF2 29 GPIO 5V PC9 30 GPIO 5V PC10 32 GPIO 5V PC11 33 GPIO 5V PF0 34 GPIO 5V PF1 35 GPIO 5V PB13 36 GPIO PB12 37 GPIO PB11 38 GPIO PF3 39 GPIO 5V PF4 40 GPIO 5V PF5 41 GPIO 5V PF6 42 GPIO 5V PF7 43 GPIO 5V RESETn 44 Reset input active low To a...

Page 77: ...CY BUSDX ADC0_EXTP VDAC0_EXT TIM0_CC0 1 TIM0_CC1 0 TIM0_CC2 31 TIM0_CDTI0 30 TIM0_CDTI1 29 TIM0_CDTI2 28 TIM1_CC0 1 TIM1_CC1 0 TIM1_CC2 31 TIM1_CC3 30 WTIM0_CC0 1 LE TIM0_OUT0 1 LE TIM0_OUT1 0 PCNT0_S0IN 1 PCNT0_S1IN 0 US0_TX 1 US0_RX 0 US0_CLK 31 US0_CS 30 US0_CTS 29 US0_RTS 28 US1_TX 1 US1_RX 0 US1_CLK 31 US1_CS 30 US1_CTS 29 US1_RTS 28 LEU0_TX 1 LEU0_RX 0 I2C0_SDA 1 I2C0_SCL 0 FRC_DCLK 1 FRC_DO...

Page 78: ... PCNT0_S0IN 4 PCNT0_S1IN 3 US0_TX 4 US0_RX 3 US0_CLK 2 US0_CS 1 US0_CTS 0 US0_RTS 31 US1_TX 4 US1_RX 3 US1_CLK 2 US1_CS 1 US1_CTS 0 US1_RTS 31 LEU0_TX 4 LEU0_RX 3 I2C0_SDA 4 I2C0_SCL 3 FRC_DCLK 4 FRC_DOUT 3 FRC_DFRAME 2 MODEM_DCLK 4 MODEM_DIN 3 MODEM_DOUT 2 PRS_CH6 4 PRS_CH7 3 PRS_CH8 2 PRS_CH9 1 ACMP0_O 4 ACMP1_O 4 LES_CH12 PA5 VDAC0_OUT0ALT OPA0_OUTALT 0 BUSCY BUSDX TIM0_CC0 5 TIM0_CC1 4 TIM0_CC...

Page 79: ...TIM0_CDTI2 4 LETIM0_OUT0 7 LETIM0_OUT1 6 PCNT0_S0IN 7 PCNT0_S1IN 6 US0_TX 7 US0_RX 6 US0_CLK 5 US0_CS 4 US0_CTS 3 US0_RTS 2 US1_TX 7 US1_RX 6 US1_CLK 5 US1_CS 4 US1_CTS 3 US1_RTS 2 LEU0_TX 7 LEU0_RX 6 I2C0_SDA 7 I2C0_SCL 6 FRC_DCLK 7 FRC_DOUT 6 FRC_DFRAME 5 MODEM_DCLK 7 MODEM_DIN 6 MODEM_DOUT 5 PRS_CH6 7 PRS_CH7 6 PRS_CH8 5 PRS_CH9 4 ACMP0_O 7 ACMP1_O 7 PB13 BUSCY BUSDX OPA2_N TIM0_CC0 8 TIM0_CC1 ...

Page 80: ... LETIM0_OUT0 10 LETIM0_OUT1 9 PCNT0_S0IN 10 PCNT0_S1IN 9 US0_TX 10 US0_RX 9 US0_CLK 8 US0_CS 7 US0_CTS 6 US0_RTS 5 US1_TX 10 US1_RX 9 US1_CLK 8 US1_CS 7 US1_CTS 6 US1_RTS 5 LEU0_TX 10 LEU0_RX 9 I2C0_SDA 10 I2C0_SCL 9 FRC_DCLK 10 FRC_DOUT 9 FRC_DFRAME 8 MODEM_DCLK 10 MODEM_DIN 9 MODEM_DOUT 8 CMU_CLK0 1 PRS_CH6 10 PRS_CH7 9 PRS_CH8 8 PRS_CH9 7 ACMP0_O 10 ACMP1_O 10 PC6 BUSBY BUSAX TIM0_CC0 11 TIM0_C...

Page 81: ...TIM0_CDTI2 16 LETIM0_OUT0 13 LETIM0_OUT1 12 PCNT0_S0IN 13 PCNT0_S1IN 12 US0_TX 13 US0_RX 12 US0_CLK 11 US0_CS 10 US0_CTS 9 US0_RTS 8 US1_TX 13 US1_RX 12 US1_CLK 11 US1_CS 10 US1_CTS 9 US1_RTS 8 LEU0_TX 13 LEU0_RX 12 I2C0_SDA 13 I2C0_SCL 12 FRC_DCLK 13 FRC_DOUT 12 FRC_DFRAME 11 MODEM_DCLK 13 MODEM_DIN 12 MODEM_DOUT 11 PRS_CH0 10 PRS_CH9 13 PRS_CH10 2 PRS_CH11 1 ACMP0_O 13 ACMP1_O 13 ETM_TD1 PC9 BUS...

Page 82: ...I1 21 WTIM0_CDTI2 19 LETIM0_OUT0 16 LETIM0_OUT1 15 PCNT0_S0IN 16 PCNT0_S1IN 15 US0_TX 16 US0_RX 15 US0_CLK 14 US0_CS 13 US0_CTS 12 US0_RTS 11 US1_TX 16 US1_RX 15 US1_CLK 14 US1_CS 13 US1_CTS 12 US1_RTS 11 LEU0_TX 16 LEU0_RX 15 I2C0_SDA 16 I2C0_SCL 15 I2C1_SDA 20 I2C1_SCL 19 FRC_DCLK 16 FRC_DOUT 15 FRC_DFRAME 14 MODEM_DCLK 16 MODEM_DIN 15 MODEM_DOUT 14 CMU_CLK0 3 PRS_CH0 13 PRS_CH9 16 PRS_CH10 5 PR...

Page 83: ...TIM0_OUT0 19 LETIM0_OUT1 18 PCNT0_S0IN 19 PCNT0_S1IN 18 US0_TX 19 US0_RX 18 US0_CLK 17 US0_CS 16 US0_CTS 15 US0_RTS 14 US1_TX 19 US1_RX 18 US1_CLK 17 US1_CS 16 US1_CTS 15 US1_RTS 14 LEU0_TX 19 LEU0_RX 18 I2C0_SDA 19 I2C0_SCL 18 FRC_DCLK 19 FRC_DOUT 18 FRC_DFRAME 17 MODEM_DCLK 19 MODEM_DIN 18 MODEM_DOUT 17 PRS_CH3 10 PRS_CH4 2 PRS_CH5 1 PRS_CH6 13 ACMP0_O 19 ACMP1_O 19 LES_CH3 PD12 VDAC0_OUT1ALT OP...

Page 84: ...IM0_OUT1 21 PCNT0_S0IN 22 PCNT0_S1IN 21 US0_TX 22 US0_RX 21 US0_CLK 20 US0_CS 19 US0_CTS 18 US0_RTS 17 US1_TX 22 US1_RX 21 US1_CLK 20 US1_CS 19 US1_CTS 18 US1_RTS 17 LEU0_TX 22 LEU0_RX 21 I2C0_SDA 22 I2C0_SCL 21 FRC_DCLK 22 FRC_DOUT 21 FRC_DFRAME 20 MODEM_DCLK 22 MODEM_DIN 21 MODEM_DOUT 20 CMU_CLK0 5 PRS_CH3 13 PRS_CH4 5 PRS_CH5 4 PRS_CH6 16 ACMP0_O 22 ACMP1_O 22 LES_CH6 GPIO_EM4WU4 PD15 VDAC0_OUT...

Page 85: ...UT1 24 PCNT0_S0IN 25 PCNT0_S1IN 24 US0_TX 25 US0_RX 24 US0_CLK 23 US0_CS 22 US0_CTS 21 US0_RTS 20 US1_TX 25 US1_RX 24 US1_CLK 23 US1_CS 22 US1_CTS 21 US1_RTS 20 US2_TX 15 US2_RX 14 US2_CLK 13 US2_CS 12 US2_CTS 11 US2_RTS 10 LEU0_TX 25 LEU0_RX 24 I2C0_SDA 25 I2C0_SCL 24 FRC_DCLK 25 FRC_DOUT 24 FRC_DFRAME 23 MODEM_DCLK 25 MODEM_DIN 24 MODEM_DOUT 23 PRS_CH0 1 PRS_CH1 0 PRS_CH2 7 PRS_CH3 6 ACMP0_O 25 ...

Page 86: ...DEM_DIN 26 MODEM_DOUT 25 CMU_CLK1 6 PRS_CH0 3 PRS_CH1 2 PRS_CH2 1 PRS_CH3 0 ACMP0_O 27 ACMP1_O 27 DBG_TDI PF4 BUSBY BUSAX TIM0_CC0 28 TIM0_CC1 27 TIM0_CC2 26 TIM0_CDTI0 25 TIM0_CDTI1 24 TIM0_CDTI2 23 TIM1_CC0 28 TIM1_CC1 27 TIM1_CC2 26 TIM1_CC3 25 LE TIM0_OUT0 28 LE TIM0_OUT1 27 PCNT0_S0IN 28 PCNT0_S1IN 27 US0_TX 28 US0_RX 27 US0_CLK 26 US0_CS 25 US0_CTS 24 US0_RTS 23 US1_TX 28 US1_RX 27 US1_CLK 2...

Page 87: ...M_DIN 28 MODEM_DOUT 27 PRS_CH0 5 PRS_CH1 4 PRS_CH2 3 PRS_CH3 2 ACMP0_O 29 ACMP1_O 29 PF6 BUSBY BUSAX TIM0_CC0 30 TIM0_CC1 29 TIM0_CC2 28 TIM0_CDTI0 27 TIM0_CDTI1 26 TIM0_CDTI2 25 TIM1_CC0 30 TIM1_CC1 29 TIM1_CC2 28 TIM1_CC3 27 LE TIM0_OUT0 30 LE TIM0_OUT1 29 PCNT0_S0IN 30 PCNT0_S1IN 29 US0_TX 30 US0_RX 29 US0_CLK 28 US0_CS 27 US0_CTS 26 US0_RTS 25 US1_TX 30 US1_RX 29 US1_CLK 28 US1_CS 27 US1_CTS 2...

Page 88: ...RX 30 US0_CLK 29 US0_CS 28 US0_CTS 27 US0_RTS 26 US1_TX 31 US1_RX 30 US1_CLK 29 US1_CS 28 US1_CTS 27 US1_RTS 26 US2_TX 20 US2_RX 19 US2_CLK 18 US2_CS 17 US2_CTS 16 US2_RTS 15 LEU0_TX 31 LEU0_RX 30 I2C0_SDA 31 I2C0_SCL 30 FRC_DCLK 31 FRC_DOUT 30 FRC_DFRAME 29 MODEM_DCLK 31 MODEM_DIN 30 MODEM_DOUT 29 CMU_CLKI0 1 CMU_CLK0 7 PRS_CH0 7 PRS_CH1 6 PRS_CH2 5 PRS_CH3 4 ACMP0_O 31 ACMP1_O 31 GPIO_EM4WU1 MGM...

Page 89: ...D10 19 PD11 20 PD12 21 PD13 22 PD14 23 PD15 24 PF0 25 PF1 26 PF2 27 PF3 28 PF4 29 PF5 30 PF6 31 PF7 Analog comparator ACMP0 digital out put ACMP1_O 0 PA0 1 PA1 2 PA2 3 PA3 4 PA4 5 PA5 6 PB11 7 PB12 8 PB13 9 PB14 10 PB15 11 PC6 12 PC7 13 PC8 14 PC9 15 PC10 16 PC11 17 PD9 18 PD10 19 PD11 20 PD12 21 PD13 22 PD14 23 PD15 24 PF0 25 PF1 26 PF2 27 PF3 28 PF4 29 PF5 30 PF6 31 PF7 Analog comparator ACMP1 d...

Page 90: ...bug interface Serial Wire viewer Output Note that this func tion is not enabled after reset and must be enabled by software to be used DBG_TDI 0 PF3 Debug interface JTAG Test Data In Note that this func tion becomes avail able after the first valid JTAG com mand is received and has a built in pull up when JTAG is active DBG_TDO 0 PF2 Debug interface JTAG Test Data Out Note that this func tion beco...

Page 91: ...4 PA5 5 PB11 6 PB12 7 PB13 8 PB14 9 PB15 10 PC6 11 PC7 12 PC8 13 PC9 14 PC10 15 PC11 16 PD9 17 PD10 18 PD11 19 PD12 20 PD13 21 PD14 22 PD15 23 PF0 24 PF1 25 PF2 26 PF3 27 PF4 28 PF5 29 PF6 30 PF7 31 PA0 Frame Controller Data Sniffer Out put GPIO_EM4WU0 0 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 0 PF7 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 0 PD14 Pin can be...

Page 92: ...SENSE channel 7 LES_CH8 0 PA0 LESENSE channel 8 LES_CH9 0 PA1 LESENSE channel 9 LES_CH10 0 PA2 LESENSE channel 10 LES_CH11 0 PA3 LESENSE channel 11 LES_CH12 0 PA4 LESENSE channel 12 LES_CH13 0 PA5 LESENSE channel 13 LETIM0_OUT0 0 PA0 1 PA1 2 PA2 3 PA3 4 PA4 5 PA5 6 PB11 7 PB12 8 PB13 9 PB14 10 PB15 11 PC6 12 PC7 13 PC8 14 PC9 15 PC10 16 PC11 17 PD9 18 PD10 19 PD11 20 PD12 21 PD13 22 PD14 23 PD15 2...

Page 93: ... 4 PA4 5 PA5 6 PB11 7 PB12 8 PB13 9 PB14 10 PB15 11 PC6 12 PC7 13 PC8 14 PC9 15 PC10 16 PC11 17 PD9 18 PD10 19 PD11 20 PD12 21 PD13 22 PD14 23 PD15 24 PF0 25 PF1 26 PF2 27 PF3 28 PF4 29 PF5 30 PF6 31 PF7 MODEM data clock out MODEM_DIN 0 PA1 1 PA2 2 PA3 3 PA4 4 PA5 5 PB11 6 PB12 7 PB13 8 PB14 9 PB15 10 PC6 11 PC7 12 PC8 13 PC9 14 PC10 15 PC11 16 PD9 17 PD10 18 PD11 19 PD12 20 PD13 21 PD14 22 PD15 2...

Page 94: ...0 15 PC11 16 PD9 17 PD10 18 PD11 19 PD12 20 PD13 21 PD14 22 PD15 23 PF0 24 PF1 25 PF2 26 PF3 27 PF4 28 PF5 29 PF6 30 PF7 31 PA0 Pulse Counter PCNT0 input num ber 1 PRS_CH0 0 PF0 1 PF1 2 PF2 3 PF3 4 PF4 5 PF5 6 PF6 7 PF7 8 PC6 9 PC7 10 PC8 11 PC9 12 PC10 13 PC11 Peripheral Reflex System PRS chan nel 0 PRS_CH1 0 PF1 1 PF2 2 PF3 3 PF4 4 PF5 5 PF6 6 PF7 7 PF0 Peripheral Reflex System PRS chan nel 1 PR...

Page 95: ...15 PC10 16 PC11 Peripheral Reflex System PRS chan nel 9 PRS_CH10 0 PC6 1 PC7 2 PC8 3 PC9 4 PC10 5 PC11 Peripheral Reflex System PRS chan nel 10 PRS_CH11 0 PC7 1 PC8 2 PC9 3 PC10 4 PC11 5 PC6 Peripheral Reflex System PRS chan nel 11 TIM0_CC0 0 PA0 1 PA1 2 PA2 3 PA3 4 PA4 5 PA5 6 PB11 7 PB12 8 PB13 9 PB14 10 PB15 11 PC6 12 PC7 13 PC8 14 PC9 15 PC10 16 PC11 17 PD9 18 PD10 19 PD11 20 PD12 21 PD13 22 P...

Page 96: ...A3 4 PA4 5 PA5 6 PB11 7 PB12 8 PB13 9 PB14 10 PB15 11 PC6 12 PC7 13 PC8 14 PC9 15 PC10 16 PC11 17 PD9 18 PD10 19 PD11 20 PD12 21 PD13 22 PD14 23 PD15 24 PF0 25 PF1 26 PF2 27 PF3 28 PF4 29 PF5 30 PF6 31 PF7 Timer 1 Capture Compare input output channel 0 TIM1_CC1 0 PA1 1 PA2 2 PA3 3 PA4 4 PA5 5 PB11 6 PB12 7 PB13 8 PB14 9 PB15 10 PC6 11 PC7 12 PC8 13 PC9 14 PC10 15 PC11 16 PD9 17 PD10 18 PD11 19 PD1...

Page 97: ...ro nous Receive USART0 Synchro nous mode Master Input Slave Out put MISO US0_TX 0 PA0 1 PA1 2 PA2 3 PA3 4 PA4 5 PA5 6 PB11 7 PB12 8 PB13 9 PB14 10 PB15 11 PC6 12 PC7 13 PC8 14 PC9 15 PC10 16 PC11 17 PD9 18 PD10 19 PD11 20 PD12 21 PD13 22 PD14 23 PD15 24 PF0 25 PF1 26 PF2 27 PF3 28 PF4 29 PF5 30 PF6 31 PF7 USART0 Asynchro nous Transmit Al so used as receive input in half duplex communication USART0...

Page 98: ... 11 PC6 12 PC7 13 PC8 14 PC9 15 PC10 16 PC11 17 PD9 18 PD10 19 PD11 20 PD12 21 PD13 22 PD14 23 PD15 24 PF0 25 PF1 26 PF2 27 PF3 28 PF4 29 PF5 30 PF6 31 PF7 USART1 Asynchro nous Transmit Al so used as receive input in half duplex communication USART1 Synchro nous mode Master Output Slave In put MOSI US2_CLK 12 PF0 13 PF1 14 PF3 15 PF4 16 PF5 17 PF6 18 PF7 30 PA5 USART2 clock in put output US2_CS 11...

Page 99: ...log Converter DAC0 output channel number 1 VDAC0_OUT1AL T OPA1_OUT ALT 0 PD12 1 PA2 2 PA4 Digital to Analog Converter DAC0 al ternative output for channel 1 WTIM0_CC0 0 PA0 1 PA1 2 PA2 3 PA3 4 PA4 5 PA5 15 PB11 16 PB12 17 PB13 18 PB14 19 PB15 26 PC6 27 PC7 28 PC8 29 PC9 30 PC10 31 PC11 Wide timer 0 Cap ture Compare in put output channel 0 WTIM0_CC1 0 PA2 1 PA3 2 PA4 3 PA5 13 PB11 14 PB12 15 PB13 1...

Page 100: ...8 PB14 9 PB15 16 PC6 17 PC7 18 PC8 19 PC9 20 PC10 21 PC11 23 PD9 24 PD10 25 PD11 26 PD12 27 PD13 28 PD14 29 PD15 30 PF0 31 PF1 Wide timer 0 Com plimentary Dead Time Insertion channel 1 WTIM0_CDTI2 3 PB11 4 PB12 5 PB13 6 PB14 7 PB15 14 PC6 15 PC7 16 PC8 17 PC9 18 PC10 19 PC11 21 PD9 22 PD10 23 PD11 24 PD12 25 PD13 26 PD14 27 PD15 28 PF0 29 PF1 30 PF2 31 PF3 Wide timer 0 Com plimentary Dead Time Ins...

Page 101: ...OUT2 OUT3 OUT4 OUT POS NEG OPA1 OUT 1X 2X 3X 4X 1Y 2Y 3Y 4Y 1X OPA1_P OPA1_N OUT1 OUT1ALT OUT1 OUT2 OUT3 OUT4 ADC_EXTP ADC_EXTN OUT0 OUT1 OPA0_N OPA0_P OPA1_N OPA1_P VDAC0_OUT0ALT OUT0ALT VDAC0_OUT0ALT OUT0ALT VDAC0_OUT0ALT OUT0ALT VDAC0_OUT1ALT OUT1ALT VDAC0_OUT1ALT OUT1ALT VDAC0_OUT0ALT OUT1ALT nX nY APORTnX APORTnY AX BY BUSAX BUSBY POS NEG OPA2 1X 2X 3X 4X 1Y 2Y 3Y 4Y 1X OPA2_P OPA2_N OUT2 OUT...

Page 102: ... Mapping Port Bus CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 APORT1X BUSAX PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT1Y BUSAY PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2X BUSBX PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2Y BUSBY PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT3X BUSCX PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 APORT3Y B...

Page 103: ...Y PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2X BUSBX PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2Y BUSBY PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT3X BUSCX PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 APORT3Y BUSCY PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4X BUSDX PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4Y BUSDY PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 MGM13S Mighty Gecko SiP Module Data Sheet Pin Definitions sil...

Page 104: ...Y PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2X BUSBX PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2Y BUSBY PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT3X BUSCX PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 APORT3Y BUSCY PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4X BUSDX PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4Y BUSDY PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 MGM13S Mighty Gecko SiP Module Data Sheet Pin Definitions sil...

Page 105: ...RT2X BUSBX PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2Y BUSBY PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT4X BUSDX PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4Y BUSDY PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 Table 7 8 IDAC0 Bus and Pin Mapping Port Bus CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 APORT1X BUS...

Page 106: ...SBY PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT3Y BUSCY PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4Y BUSDY PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 OPA0_P APORT1X BUSAX PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT2X BUSBX PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT3X BUSCX PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 APORT4X BUSDX PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 MGM13S Mighty Gecko SiP Module Data Sheet Pin Defini...

Page 107: ...A2 PA0 PD14 PD12 PD10 OPA1_P APORT1X BUSAX PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT2X BUSBX PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT3X BUSCX PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 APORT4X BUSDX PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 OPA2_N APORT1Y BUSAY PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2Y BUSBY PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT3Y BUSCY PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4Y BUSDY PB14 PB...

Page 108: ...0 PD14 PD12 PD10 OPA2_P APORT1X BUSAX PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT2X BUSBX PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT3X BUSCX PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 APORT4X BUSDX PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 VDAC0_OUT0 OPA0_OUT APORT1Y BUSAY PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2Y BUSBY PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT3Y BUSCY PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4Y BUSDY...

Page 109: ...CH3 CH2 CH1 CH0 VDAC0_OUT1 OPA1_OUT APORT1Y BUSAY PF7 PF5 PF3 PF1 PC11 PC9 PC7 APORT2Y BUSBY PF6 PF4 PF2 PF0 PC10 PC8 PC6 APORT3Y BUSCY PB15 PB13 PB11 PA5 PA3 PA1 PD15 PD13 PD11 PD9 APORT4Y BUSDY PB14 PB12 PA4 PA2 PA0 PD14 PD12 PD10 MGM13S Mighty Gecko SiP Module Data Sheet Pin Definitions silabs com Building a more connected world Rev 1 0 109 ...

Page 110: ...ons Figure 8 1 MGM13S Package Dimensions Dimension MIN NOM MAX A 1 20 1 30 1 40 A1 0 26 0 30 0 34 A2 0 95 1 00 1 05 b 0 27 0 32 0 37 MGM13S Mighty Gecko SiP Module Data Sheet Package Specifications silabs com Building a more connected world Rev 1 0 110 ...

Page 111: ...1 0 11 0 16 0 21 L2 0 34 0 39 0 44 L3 0 24 0 29 0 34 L4 0 14 0 19 0 24 L5 0 62 0 67 0 72 eD1 1 20 BSC eD2 2 40 BSC eD3 0 07 BSC eD4 1 50 BSC eE1 0 30 BSC eE2 0 20 BSC eE3 1 60 BSC eE4 1 65 BSC eE5 0 80 BSC aaa 0 10 bbb 0 10 ccc 0 10 ddd 0 10 eee 0 10 MGM13S Mighty Gecko SiP Module Data Sheet Package Specifications silabs com Building a more connected world Rev 1 0 111 ...

Page 112: ...Outline MO 220 5 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components 6 Hatching lines means package shielding area 7 Solid pattern 3 1x3 1mm shows non shielding area including its side walls For side wall borderline between shielding area and not shielding area could not be defined clearly like top side MGM13S Mighty Gecko SiP Module Data Sheet Pa...

Page 113: ...e the X Y cordinates of pads relative to the origin are shown in Table 8 1 MGM13S Pad Coordinates and Sizing on page 114 The origin is the center point of pin number 47 It is very important to align the antenna area relative to the module pads precisely Figure 8 2 MGM13S Recommended Antenna Clearance MGM13S Mighty Gecko SiP Module Data Sheet Package Specifications silabs com Building a more connec...

Page 114: ... 0 32 x 0 48 1 0 1 60 2 0 2 10 9 0 5 60 10 0 60 5 75 19 5 10 5 75 20 5 70 5 60 31 5 70 0 10 32 5 10 0 05 36 5 10 1 65 45 0 60 1 65 49 0 1 00 46 2 92 0 50 1 65 3 70 0 67 x 0 67 51 4 05 3 70 MGM13S Mighty Gecko SiP Module Data Sheet Package Specifications silabs com Building a more connected world Rev 1 0 114 ...

Page 115: ... 5 50 BSC D2 3 70 BSC D3 4 00 BSC D4 0 05 BSC D5 1 65 BSC eD1 1 00 BSC eD2 0 60 BSC eD3 0 15 BSC e 0 50 BSC E1 5 70 BSC E2 5 10 BSC E3 3 60 BSC E4 2 92 BSC E5 1 65 BSC E6 4 50 BSC E7 4 50 BSC L 0 48 BSC MGM13S Mighty Gecko SiP Module Data Sheet Package Specifications silabs com Building a more connected world Rev 1 0 115 ...

Page 116: ...trapezoidal walls should be used to assure good solder paste release 4 The stencil thickness should be 0 100mm 4 mils 5 The stencil aperture to land pad size recommendation is 70 paste coverage 6 Above notes and stencil design are shared as recommendations only A customer or user may find it necessary to use different parameters and fine tune their SMT process as required for their application and...

Page 117: ...ons Marking Explanation MGM13Sxxx Model Number FCCIDQOQ13 FCC Certification ID IC5123A 13 IC5123A 13 R CRM BGT 13 KC Korea Certification ID YWWTTTT 1 Y Manufacturing Year 2 WW Manufacturing Work Week 3 TTTT Trace Code MGM13S Mighty Gecko SiP Module Data Sheet Package Specifications silabs com Building a more connected world Rev 1 0 117 ...

Page 118: ...inless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release Recommended stencil thickness is 0 100mm 4 mils Refer to the recommended PCB land pattern for an example stencil aperture size For further recommendation please refer to the JEDEC IPC J STD 020 IPC SM 782 and IPC 7351 guidelines Above notes and stencil design are shared as ...

Page 119: ...e essential requirements and other relevant requirements of the Radio Equipment Di rective RED 2014 53 EU Please note that every application using the MGM13S02 will need to perform the radio EMC tests on the end product according to EN 301 489 17 It is ultimately the responsibility of the manufacturer to ensure the compliance of the end product The specific product assembly may have an impact to R...

Page 120: ...s at all times With MGM13S02 the antenna s must be installed such that a minimum separation distance of 0 mm is maintained between the radiator antenna and all persons at all times The transmitter module must not be co located or operating in conjunction with any other antenna or transmitter except in accord ance with FCC multi transmitter product procedures Important Note In the event that the ab...

Page 121: ...bove is maintained between the radiator an tenna and all persons at all times The transmitter module must not be co located or operating in conjunction with any other antenna or transmitter As long as the two conditions above are met further transmitter testing will not be required However the OEM integrator is still respon sible for testing their end product for any additional compliance requirem...

Page 122: ...avoisinante ce à tout moment Le module émetteur ne doit pas être localisé ou fonctionner avec une autre antenne ou un autre transmetteur que celle indiquée plus haut Tant que les deux conditions ci dessus sont respectées il n est pas nécessaire de tester ce transmetteur de façon plus poussée Ce pendant il incombe à l intégrateur OEM de s assurer de la bonne conformité du produit fini avec les autr...

Page 123: ...e users of the combination of host and radio module to verify if they are actually using a radio device which is approved for use in Japan Certification Text to be Placed on the Outside Surface of the Host Equipment Translation of the text This equipment contains specified radio equipment that has been certified to the Technical Regulation Conformity Certification under the Radio Law The Giteki ma...

Page 124: ...tent Added V2 part numbers to Table 2 1 Ordering Information on page 3 Updated 4 1 Electrical Characteristics with latest characterization data and test limits 5 1 Typical MGM13S Connections Added optional 32 768 kHz crystal connection 5 1 Typical MGM13S Connections Corrected RTS CTS naming on Host CPU for UART connection 5 1 Typical MGM13S Connections Corrected TCK TMS order on standard ARM Corte...

Page 125: ... or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significan...

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