Silicon Laboratories MGM13S Series, Manual, Page: 66 / 125

4.1.22 USART SPI
SPI Master Timing
Table 4.41. SPI Master Timing
Parameter Symbol Test Condition Min Typ Max Unit
SCLK period
1 2 3 t
SCLK
2 *
t
HFPERCLK
— — ns
CS to MOSI
1 2 t
CS_MO
-12.5 — 14 ns
SCLK to MOSI
1 2 t
SCLK_MO
-8.5 — 10.5 ns
MISO setup time
1 2 t
SU_MI
IOVDD = 1.62 V 90 — — ns
IOVDD = 3.0 V 42 — — ns
MISO hold time
1 2 t
H_MI
-9 — — ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of V
DD
(figure shows 50% of V
DD
).
3. t
HFPERCLK
is one period of the selected HFPERCLK.
CS
SCLK
CLKPOL = 0
MOSI
MISO
t
CS_MO
t
H_MI
t
SU_MI
t
SCKL_MO
t
SCLK
SCLK
CLKPOL = 1
Figure 4.1. SPI Master Timing Diagram
MGM13S Mighty Gecko SiP Module Data Sheet
Electrical Specifications
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