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2.2.1 Layout Design Guidelines (sub-GHz)
• Due to the differential TX/RX pins of the sub-GHz EFR32 Series 1 wireless MCU, the traces that connect the first TX/RX compo-
nent(s) with the TX output / RX input of the chip must be routed on different layers. To decrease the parasitic capacitance towards
the ground, it is recommended to apply a keepout on all inner layers beneath the area of the RX matching network. On the first inner
layer, the area beneath the remainder sub-GHz matching network (balun and low-pass filter) should be filled with ground metal.
Traces can be routed beneath the area of the balun and low-pass filter sections on all other inner layers.
• Use the shortest traces possible to connect the first RX matching network component with the RX input pins of the chip. As a result,
the first TX matching network components can be connected only with relatively long traces.
• No traces should be routed on the layer beneath the traces that connects the first TX matching components with TX pins.
• It is recommended to add an isolating ground metal with many vias between the 2.4 GHz and sub-GHz matching networks.
The following figures illustrate layer consistency around the area of the matching networks on the layout of the EFR32 Series 1 Dual-
band Reference Radio Board.
Figure 2.9. Layout of the Matching Area on the EFR32 Series 1 Dual-band Reference Layout — Top layer
Figure 2.10. Layout of the Matching Area on the EFR32 Series 1 Dual-band Reference Layout — Inner layer 1
Figure 2.11. Layout of the Matching Area on the EFR32 Series 1 Dual-band Reference Layout — Inner layer 2
AN928.1: EFR32 Series 1 Layout Design Guide
Guidelines for Layout Design When Using EFR32 Wireless MCUs
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