Rev 2.0 | SC5309A & SC5310A
Hardware Manual
SignalCore, Inc.
30
SC5309A & SC5310A Hardware Manual
Bits Type Name
Width Description
[50:48]
W
Parameter
3
0 = RF frequency
1 = IF1 frequency
2 = IF2 frequency Filt#0 path
3 = IF2 frequency Filt#1 path
4 = IF3 frequency
5 = LO2 pll step size
6 = LO3 pll step size
[55:51]
W
Unused
5
Set to zeros
[7:0]
R
Read back byte
8
Read 1 byte back is required for PXIe and RS232
Register 0x1B SYNTH_MODE (2 Bytes)
This register configures the PLL loop gain of the local oscillator synthesizers. It also enables or
disables faster tuning of the YIG based oscillator of LO1.
Bytes written 2
Bytes read 1
Bits Type Name
Width Description
[1:0]
WO
Loop Gain
2
0 = Low loop gain, improves phase noise > 50 kHz
1 = Normal loop gain
2 = High loop gain, improves phase noise < 50 kHz
[7:2]
WO
Unused
5
Set to zeros
[7:0]
RO
Read back byte
8
Read 1 byte back is required for PXIe and RS232
Register 0x1C SYNTH_SELF_CAL
This register will start the YIG synthesizer calibration. Note that although the calibration procedure
takes about 6-8 seconds to complete, the register returns a byte almost immediately.
Bytes written 2
Bytes read 1
Bits Type Name
Width Description
[7:0]
W
Unused
8
Set to zeros