ICD-4000-OEM
© SightLine Applications, Inc.
14
8.6
Synchronization Signals
•
VIN_VSYNC vertical sync: A rising edge (default) indicates the start of a new frame. This can be
configured through acquisition parameters to falling edge.
•
VIN_HSYNC horizontal sync: A rising edge (default) indicates the start of a new line. This can be
configured through the acquisition parameters to falling edge.
•
VIN_ACLK pixel clock: Pixel data is sampled on the rising edge. Maximum input rate is 74.25 MHz.
Clock edge is not currently configurable through the acquisition parameters.
•
VIN_FLD (
not used
): The 4000 does not support Field information. MIPI image type does not
provide for an Interlaced flag in the MIPI packet header. For BT.656 (analog video) inputs, the 4000-
OEM FPGA takes the interlaced data in BT.656 and generates a progressive frame with two fields
per frame. It then de-fields these frames during processing. This is not currently supported for
other formats, e.g.,1080i is not supported.
•
VIN_DE (
not used
): This is line enable or line valid. Not currently supported on the 4000-OEM.
Embedded Sync
In this case all synchronization information is in the embedded sync codes - only the
pixel clock and the data stream are used.
•
BT.1120 (HD, 720/1080P)
•
BT.656. (SD – 525/625 lines)
8.7
Camera Resolution and Pixel Clock Requirements
The 4000-OEM Snapdragon processor will acquire MIPI and USB format camera data. The camera data
format generated by the adapter boards (3000-HDMI, 3000 SDI, etc.) must be converted to MIPI
format for acquisition. This conversion is done using a Lattice FPGA, which adds requirements to the
pixel clock rate and blanking from the camera.
The following sections help clarify which FPGA version to use for new camera support.
The Lattice MIPI DPhy PLL maximum input clock is 150 MHz. This is different than the specification
of the Lattice chip for external clock inputs. See the frequency in
Table 16
and
Table 17
for each
version. For additional details on the MIPI interface, clocks, and timing see
. This
limits the maximum input pixel clock of the system to 150 MHz.
8.8
Camera Pixel Clock Rate and MIPI Conversion
MIPI is a packetized serial bitstream with a clock rate that is proportional to the camera pixel clock
rate. The MIPI clock rate additionally depends on the number of MIPI lanes used (1,2,4) and the bit
depth of the camera data.
The SightLine Phase Lock Loop (PLL) in the lattice FPGA generates the correct MIPI clock based on the
relevant parameters. This PLL has a limited range of camera pixel clock frequencies that it can lock
onto. The lock range is a factor of ~2 on the camera pixel input clock. For example, a PLL generated
with a center frequency of 40 MHz will work for camera clock frequencies of approximately 20 to 80
MHz.
