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[31:2]

Reserved

UART Interrupt Pending Register (

)

Register Offset

0x14

Bits

Field Name

Attr.

Rst.

Description

txwm

Transmit watermark interrupt pending

rxwm

Receive watermark interrupt pending

[31:2]

Reserved

17.9

Baud Rate Divisor Register (

div

)

The read-write,

div_width

-bit

div

for both Tx and Rx channels. The relationship between the input clock and baud rate is given by
the following formula:

The input clock is the bus clock

tlclk

. The reset value of the register is set to

div_init

, which

is tuned to provide a 115200 baud output out of reset given the expected frequency of

tlclk

Table 56 shows divisors for some common core clock rates and commonly used baud rates.
Note that the table shows the divide ratios, which are one greater than the value stored in the

div

Table 56:

Common baud rates (MIDI=31250, DMX=250000) and required

divide values to achieve them with given bus clock frequencies. The divide val-

ues are one greater than the value stored in the

div

register.

tlclk

(MHz)

Target Baud (Hz)

Divisor

Actual Baud (Hz)

Error (%)

31250

115200

117647

2.1

31250

512

31250

115200

139

115107

0.08

250000

Table 54:

UART Interrupt Enable Register

Table 55:

UART Interrupt Pending Register

Chapter 17 Universal Asynchronous Receiver/Transmitter

SiFive FE310-G000 Manual: v3p2

© SiFive, Inc.

Page 80

Summary of Contents for FE310-G000

Page 1: ...SiFive FE310 G000 Manual v3p2 SiFive Inc ...

Page 2: ... of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation indirect incidental spe cial exemplary or consequential damages SiFive reserves the right to make changes without further notice to any products herein Release Information Version Date Changes v3p2 March 25 2021 Added Creative Commons license v3p1 August 22 2019 Fixed ...

Page 3: ...elevant E31 Core Complex and E300 Plat form information 1 0 3 July 24 2017 Correct DWAKEUP_N and AON_PMU_OUT_0 pin assignments 1 0 2 June 12 2017 Clarify that QFN48 is the 6x6 Standard format 1 0 1 December 20 2016 Add QFN48 Package Pinout Add Configuration String Rename chip to FE310 G000 1 0 November 29 2016 HiFive1 release ...

Page 4: ...th Modulation 11 1 10 Debug Support 11 2 List of Abbreviations and Terms 13 3 E31 RISC V Core 15 3 1 Instruction Memory System 15 3 2 Instruction Fetch Unit 16 3 3 Execution Pipeline 16 3 4 Data Memory System 17 3 5 Atomic Memory Operations 17 3 6 Hardware Performance Monitor 17 4 Memory Map 18 5 Boot Process 20 5 1 Non volatile Code Options 20 5 1 1 Gate ROM GROM 20 5 1 2 Mask ROM MROM 20 5 1 3 O...

Page 5: ... 28 6 8 Alternate Low Frequency Clock LFALTCLK 29 6 9 Clock Summary 29 7 Power Modes 31 7 1 Run Mode 31 7 2 Wait Mode 31 7 3 Sleep Mode 31 8 Interrupts 33 8 1 Interrupt Concepts 33 8 2 Interrupt Operation 34 8 2 1 Interrupt Entry and Exit 34 8 3 Interrupt Control Status Registers 35 8 3 1 Machine Status Register mstatus 35 8 3 2 Machine Trap Vector mtvec 36 8 3 3 Machine Interrupt Enable mie 36 8 ...

Page 6: ... OTP Peripheral 49 11 1 Memory Map 49 11 2 Programmed I O lock register otp_lock 50 11 3 Programmed I O Sequencing 51 11 4 Read sequencer control register otp_rsctrl 51 11 5 OTP Programming Warnings 52 11 6 OTP Programming Procedure 52 12 Always On AON Domain 53 12 1 AON Power Source 54 12 2 AON Clocking 54 12 3 AON Reset Unit 54 12 4 External Reset Circuit 54 12 5 Reset Cause 55 12 6 Watchdog Tim...

Page 7: ...3 14 3 PMU Key Register pmukey 64 14 4 PMU Program 65 14 5 Initiate Sleep Sequence Register pmusleep 66 14 6 Wakeup Signal Conditioning 66 14 7 PMU Interrupt Enables pmuie and Wakeup Cause pmucause 66 15 Real Time Clock RTC 68 15 1 RTC Count Registers rtccounthi rtccountlo 68 15 2 RTC Configuration Register rtccfg 69 15 3 RTC Compare Register rtccmp 70 16 General Purpose Input Output Controller GP...

Page 8: ...emory Map 83 18 4 Serial Clock Divisor Register sckdiv 84 18 5 Serial Clock Mode Register sckmode 85 18 6 Chip Select ID Register csid 85 18 7 Chip Select Default Register csdef 86 18 8 Chip Select Mode Register csmode 86 18 9 Delay Control Registers delay0 and delay1 87 18 10 Frame Format Register fmt 88 18 11 Transmit Data Register txdata 89 18 12 Receive Data Register rxdata 90 18 13 Transmit W...

Page 9: ...pts 103 20 Debug 104 20 1 Debug CSRs 104 20 1 1 Trace and Debug Register Select tselect 105 20 1 2 Trace and Debug Data Registers tdata1 3 105 20 1 3 Debug Control and Status Register dcsr 106 20 1 4 Debug PC dpc 106 20 1 5 Debug Scratch dscratch 106 20 2 Breakpoints 106 20 2 1 Breakpoint Match Control Register mcontrol 107 20 2 2 Breakpoint Match Address Register maddress 109 20 2 3 Breakpoint Ex...

Page 10: ...21 2 Resetting JTAG Logic 113 21 3 JTAG Clocking 113 21 4 JTAG Standard Instructions 114 21 5 JTAG Debug Commands 114 22 References 115 SiFive FE310 G000 Manual v3p2 SiFive Inc Page 7 ...

Page 11: ...0nm process This manual serves as an architectural reference and integration guide for the FE310 G000 The FE310 G000 is compatible with all applicable RISC V standards and this document should be read together with the official RISC V user level privileged and external debug architecture specifications 1 1 FE310 G000 Overview Figure 1 shows the overall block diagram of the FE310 G000 A feature sum...

Page 12: ... MOFF Core 3 3V MOFF Pads Core Reset Sync corerst pmu_out_1 psdlfaltclk psdlfaltclksel PWM2 16 bit Figure 1 FE310 G000 top level block diagram Table 1 FE310 G000 Feature Summary Feature Description Available in QFN48 RISC V Core 1 E31 RISC V cores with machine mode only 16 KiB 2 way L1 I cache and 16 KiB data tightly integrated mem ory DTIM Interrupts Software and timer interrupts 51 peripheral in...

Page 13: ... platform level interrupt controller PLIC which supports 51 global interrupts with 7 priority levels The FE310 G000 also provides the standard RISC V machine mode timer and software interrupts via the Core Local Interruptor CLINT Interrupts are described in Chapter 8 The CLINT is described in Chapter 9 The PLIC is described in Chapter 10 1 4 On Chip Memory System The E31 core has a n 2 way set ass...

Page 14: ...I There are 3 serial peripheral interface SPI controllers Each controller provides a means for serial communication between the FE310 G000 and off chip devices like quad SPI Flash mem ory Each controller supports master only operation over single lane dual lane and quad lane protocols Each controller supports burst reads of 32 bytes over TileLink to accelerate instruc tion cache refills 1 SPI cont...

Page 15: ...Debug support is described in detail in Chapter 20 and the debug interface is described in Chapter 21 Chapter 1 Introduction SiFive FE310 G000 Manual v3p2 SiFive Inc Page 12 ...

Page 16: ...d Memory ITIM Instruction Tightly Integrated Memory JTAG Joint Test Action Group LIM Loosely Integrated Memory Used to describe memory space delivered in a SiFive Core Complex but not tightly integrated to a CPU core PMP Physical Memory Protection PLIC Platform Level Interrupt Controller The global interrupt controller in a RISC V system TileLink A free and open interconnect standard originally de...

Page 17: ...gnored and reads should ignore the value returned WLRL Write Legal Read Legal field A register field that should only be written with legal values and that only returns legal value if last written with a legal value WPRI Writes Preserve Reads Ignore field A register field that might contain unknown information Reads should ignore the value returned but writes to the whole register should preserve ...

Page 18: ...ry system consists of a dedicated 16 KiB 2 way set associative instruction cache The access latency of all blocks in the instruction memory system is one clock cycle The instruction cache is not kept coherent with the rest of the platform memory system Writes to instruction memory must be synchronized with the instruction fetch stream by executing a FENCE I instruction The instruction cache has a ...

Page 19: ...ency There are several exceptions LW has a two cycle result latency assuming a cache hit LH LHU LB and LBU have a three cycle result latency assuming a cache hit CSR reads have a three cycle result latency MUL MULH MULHU and MULHSU have a 5 cycle result latency DIV DIVU REM and REMU have between a 2 cycle and 33 cycle result latency depending on the operand values The pipeline only interlocks on r...

Page 20: ...erved and store conditional instructions are only supported on cached regions hence generate an access exception on DTIM and other uncached memory regions See The RISC V Instruction Set Manual Volume I User Level ISA Version 2 1 for more infor mation on the instructions added by this extension 3 6 Hardware Performance Monitor The FE310 G000 supports a basic hardware performance monitoring facility...

Page 21: ...KiB 0x0000_2000 0x0001_FFFF Reserved 0x0002_0000 0x0002_1FFF R XC OTP Memory Region 8 KiB 0x0002_2000 0x01FF_FFFF Reserved On Chip Non Volatile Memory 0x0200_0000 0x0200_FFFF RW A CLINT 0x0201_0000 0x0BFF_FFFF Reserved 0x0C00_0000 0x0FFF_FFFF RW A PLIC 0x1000_0000 0x1000_7FFF RW A AON 0x1000_8000 0x1000_FFFF RW A PRCI 0x1001_0000 0x1001_0FFF RW A OTP Control 0x1001_1000 0x1001_1FFF Reserved 0x1001...

Page 22: ..._4000 0x1002_4FFF RW A QSPI 1 0x1002_5000 0x1002_5FFF RW A PWM 1 0x1002_6000 0x1003_3FFF Reserved 0x1003_4000 0x1003_4FFF RW A QSPI 2 0x1003_5000 0x1003_5FFF RW A PWM 2 0x1003_6000 0x1FFF_FFFF Reserved 0x2000_0000 0x3FFF_FFFF R XCA QSPI 0 Flash 512 MiB 0x4000_0000 0x7FFF_FFFF Reserved Off Chip Non Volatile Memory 0x8000_0000 0x8000_3FFF RWXCA DTIM 16 KiB 0x8000_4000 0xFFFF_FFFF Reserved On Chip Vo...

Page 23: ...h is an illegal instruction causing another trap hence caus ing the processor to spin in a trap loop on any fetch to address 0 The trap loop is used to hold the processor when waiting for the debugger to download code to be executed The debugger can issue a debug interrupt which causes the processor to jump to the debug interrupt handler in debug ROM which in turn jumps to the code written to the ...

Page 24: ...icated QSPI flash controller connects to external SPI flash devices that are used for execute in place code SPI flash is not available in certain scenarios such as package testing or board designs not using SPI flash e g just using on chip OTP Off chip SPI devices can vary in number of supported I O bits 1 2 or 4 SPI flash bits contain all 1s prior to programming 5 2 Reset and Trap Vectors FE310 G...

Page 25: ... AON block Chapter 12 or the PRCI block Section 6 2 6 1 Clock Generation Overview Figure 2 FE310 G000 clock generation scheme Figure 2 shows an overview of the FE310 G000 clock generation scheme Most digital clocks on the chip are divided down from a central high frequency clock hfclk produced from either the PLL or an on chip trimmable oscillator The PLL can be driven from either the on chip osci...

Page 26: ...p for the PRCI on the FE310 G000 Offset Name Description 0x0 hfrosccfg Ring Oscillator Configuration and Status 0x4 hfxosccfg Crystal Oscillator Configuration and Status 0x8 pllcfg PLL Configuration and Status 0xC plloutdiv PLL Final Divide Configuration 6 3 Internal Trimmable Programmable 72 MHz Oscillator HFROSC An internal trimmable high frequency ring oscillator HFROSC is used to provide the d...

Page 27: ... reset to 16 the middle of the adjustable range and the divider is reset to divide by 5 hfroscdiv 4 which gives a nominal 13 8 MHz 50 output frequency The value of hfrosctrim that most closely achieves an 72 MHz clock output at nominal condi tions 1 8 V at 25 C is determined by manufacturing time calibration and is stored in on chip OTP storage Upon reset software in the processor boot sequence ca...

Page 28: ...t can be cleared to turn off the crystal driver and reduce power consumption The hfxoscrdy bit indicates if the crystal oscillator output is ready for use The hfxoscen bit must also be turned on to use the HFXOSC input pad to connect an external clock source 6 5 Internal High Frequency PLL HFPLL The PLL generates a high frequency clock by multiplying a mid frequency reference source clock either t...

Page 29: ...Figure 3 Controlling the FE310 G000 PLL output frequency The pllr 1 0 field encodes the reference clock divide ratio as a 2 bit binary value where the value is one less than the divide ratio i e 00 1 11 4 The frequency of the output of the refer ence divider refr must lie between 6 12 MHz The pllf 5 0 field encodes the PLL VCO multiply ratio as a 6 bit binary value signifying a divide ratio of i e...

Page 30: ...otherwise When pllsel is clear the hfroscclk directly drives hfclk The pllsel bit is clear on wakeup reset The pllcfg register is reset to bypass and power off the PLL pllbypass 1 input driven from external HFXOSC oscillator pllrefsel 1 PLL not driving system clock pllsel 0 and the PLL ratios are set to R 2 F 64 and Q 8 pllr 01 pllf 011111 pllq 11 The PLL provides a lock signal which is set when t...

Page 31: ...by1 1 6 7 Internal Programmable Low Frequency Ring Oscillator LFROSC A second programmable ring oscillator LFROSC is used to provide an internal low frequency 32 kHz clock source The LFROSC can generate frequencies in the range 1 5 230 kHz 45 The lfrosccfg register lives in the AON block as shown in Table 31 At power on reset the LFROSC resets to selecting the middle tap lfrosctrim 16 and 5 lfrosc...

Page 32: ...E310 G000 and their initial reset conditions At power on reset the AON domain lfclk is clocked by either the LFROSC or psdlfaltclk as selected by psdlfaltclksel At wakeup reset the MOFF domain hfclk is clocked by the HFROSC Table 11 FE310 G000 Clock Sources Frequency Name Reset Source Reset Min Max Notes AON Domain LFROSC lfroscrst 32 kHz 1 5 kHz 230 kHz 45 psdlfaltclk 0 kHz 500 kHz When selected ...

Page 33: ...Table 11 FE310 G000 Clock Sources PLL hfclkrst OFF 0 375 MHz 384 MHz JTAG TCK OFF 0 MHz 16 MHz Chapter 6 Clock Generation SiFive FE310 G000 Manual v3p2 SiFive Inc Page 30 ...

Page 34: ...ipeline All state is preserved in the system The processor will resume in Run mode when there is a local interrupt pending or when the PLIC sends an interrupt notification The processor may also exit wait mode for other events and software must check system status when exiting wait mode to determine the correct course of action 7 3 Sleep Mode Sleep mode is entered by writing to a memory mapped reg...

Page 35: ...e the core and can interrogate the PMU pmucause register to determine the cause of reset and can recover pre sleep state from the backup registers The processor always initially runs from the HFROSC at the default setting and must reconfigure clocks to run from an alternate clock source HFXOSC or PLL or at a different setting on the HFROSC Because the FE310 G000 has no internal power regulator the...

Page 36: ...are required to determine the cause of the interrupt Software and timer interrupts are local interrupts generated by the Core Local Interruptor CLINT The FE310 G000 contains no other local interrupt sources Global interrupts by contrast are routed through a Platform Level Interrupt Controller PLIC which can direct interrupts to any hart in the system via the external interrupt Decoupling global in...

Page 37: ...status MIE is copied into mcause MPIE and then mstatus MIE is cleared effectively disabling interrupts The privilege mode prior to the interrupt is encoded in mstatus MPP The current pc is copied into the mepc register and then pc is set to the value specified by mtvec as defined by the mtvec MODE described in Table 14 At this point control is handed over to software in the interrupt handler with ...

Page 38: ...A summary of the mstatus fields related to interrupts in the FE310 G000 is provided in Table 12 Note that this is not a complete description of mstatus as it contains fields unrelated to interrupts For the full description of mstatus please consult the The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 Table 12 FE310 G000 mstatus Register partial Machine Status Regist...

Page 39: ...byte alignment Table 14 Encoding of mtvec MODE MODE Field Encoding mtvec MODE Value Name Description 0x0 Direct All exceptions set pc to BASE 1 Reserved See Table 13 for a description of the mtvec register See Table 14 for a description of the mtvec MODE field See Table 18 for the FE310 G000 interrupt exception code values Mode Direct When operating in direct mode all synchronous exceptions and as...

Page 40: ...pt Pending mip The machine interrupt pending mip register indicates which interrupts are currently pending The mip register is described in Table 16 Table 16 mip Register Machine Interrupt Pending Register CSR mip Bits Field Name Attr Description 2 0 Reserved WIRI 3 MSIP RO Machine Software Interrupt Pending 6 4 Reserved WIRI 7 MTIP RO Machine Timer Interrupt Pending 10 8 Reserved WIRI 11 MEIP RO ...

Page 41: ...able 17 for more details about the mcause register Refer to Table 18 for a list of synchro nous exception codes Table 17 mcause Register Machine Cause Register CSR mcause Bits Field Name Attr Description 9 0 Exception Code WLRL A code identifying the last exception 30 10 Reserved WLRL 31 Interrupt WARL 1 if the trap was caused by an interrupt 0 otherwise Table 18 mcause Exception Codes Interrupt E...

Page 42: ... Machine software interrupts Machine timer interrupts 8 5 Interrupt Latency Interrupt latency for the FE310 G000 is 4 cycles as counted by the numbers of cycles it takes from signaling of the interrupt to the hart to the first instruction fetch of the handler Global interrupts routed through the PLIC incur additional latency of 3 cycles where the PLIC is clocked by coreClk This means that the tota...

Page 43: ...hitecture Version 1 10 9 1 CLINT Memory Map Table 19 shows the memory map for CLINT on SiFive FE310 G000 Table 19 CLINT Register Map Address Width Attr Description Notes 0x2000000 4B RW msip for hart 0 MSIP Registers 1 bit wide 0x2004008 0x200bff7 Reserved 0x2004000 8B RW mtimecmp for hart 0 MTIMECMP Registers 0x2004008 0x200bff7 Reserved 0x200bff8 8B RW mtime Timer Register 0x200c000 Reserved SiF...

Page 44: ...processor communication in multi hart systems as harts may write each other s msip bits to effect interprocessor interrupts 9 3 Timer Registers mtime is a 64 bit read write register that contains the number of cycles counted from the rtcclk input described in Chapter 12 A timer interrupt is pending whenever mtime is greater than or equal to the value in the mtimecmp register The timer interrupt is...

Page 45: ...PLIC control registers is shown in Table 20 The PLIC memory map has been designed to only require naturally aligned 32 bit memory accesses Table 20 SiFive PLIC Register Map Only naturally aligned 32 bit memory accesses are required PLIC Register Map Address Width Attr Description Notes 0x0C00_0000 Reserved 0x0C00_0004 4B RW source 1 priority 0x0C00_00CC 4B RW source 51 priority See Section 10 3 fo...

Page 46: ...t 0 M Mode claim com plete See Section 10 7 for more information 0x0C20_0008 Reserved 0x1000_0000 End of PLIC Memory Map 10 2 Interrupt Sources The FE310 G000 has 51 interrupt sources These are driven by various on chip devices as listed in Table 21 These signals are positive level triggered In the PLIC as specified in The RISC V Instruction Set Manual Volume II Privileged Architec ture Version 1 ...

Page 47: ...description Table 22 PLIC Interrupt Priority Registers PLIC Interrupt Priority Register priority Base Address 0x0C00_0000 4 Interrupt ID Bits Field Name Attr Rst Description 2 0 Priority RW X Sets the priority for a given global inter rupt 31 3 Reserved RO 0 10 4 Interrupt Pending Bits The current status of the interrupt source pending bits in the PLIC core can be read from the pending array organ...

Page 48: ...Address 0x0C00_1004 Bits Field Name Attr Rst Description 0 Interrupt 32 Pend ing RO 0 Pending bit for global interrupt 32 19 Interrupt 51 Pend ing RO 0 Pending bit for global interrupt 51 31 20 Reserved WIRI X 10 5 Interrupt Enables Each global interrupt can be enabled by setting the corresponding bit in the enables registers The enables registers are accessed as a contiguous array of 2 32 bit wor...

Page 49: ...2 for Hart 0 M Mode Base Address 0x0C00_2004 Bits Field Name Attr Rst Description 0 Interrupt 32 Enable RW X Enable bit for global interrupt 32 19 Interrupt 51 Enable RW X Enable bit for global interrupt 51 31 20 Reserved RO 0 10 6 Priority Thresholds The FE310 G000 supports setting of an interrupt priority threshold via the threshold register The threshold is a WARL field where the FE310 G000 sup...

Page 50: ...10 G000 hart can perform a claim at any time even if the MEIP bit in its mip Table 16 register is not set The claim operation is not affected by the setting of the priority threshold register 10 8 Interrupt Completion A FE310 G000 hart signals it has completed executing an interrupt handler by writing the inter rupt ID it received from the claim to the claim complete register Table 28 The PLIC doe...

Page 51: ...rupt Claim Complete for Hart 0 M Mode RW X A read of zero indicates that no inter rupts are pending A non zero read contains the id of the highest pending interrupt A write to this register signals completion of the interrupt id written Chapter 10 Platform Level Interrupt Controller PLIC SiFive FE310 G000 Manual v3p2 SiFive Inc Page 48 ...

Page 52: ...k is running Programmed I O reads and writes are sequenced entirely by software 11 1 Memory Map The memory map for the OTP control registers is shown in Table 29 The control register mem ory map has been designed to only require naturally aligned 32 bit memory accesses The OTP controller also contains a read sequencer which exposes the OTP s contents as a read exe cute only memory mapped device Of...

Page 53: ...n 0 immedi ately The otp_lock should be acquired before writing to any other control register Software can attempt to acquire the lock by storing 1 to otp_lock If a memory mapped read is in progress the lock will not be acquired and will retain the value 0 Software can check if the lock was suc cessfully acquired by loading otp_lock and checking that it has the value 1 After a programmed I O seque...

Page 54: ...s set by a programma ble clock divider The divider is controlled by the otp_rsctrl register the layout of which is shown in Table 30 The number of clock cycles in each phase is given by and the width of each phase may be optionally scaled by 3 That is the number of controller clock cycles in the address setup phase is given by the expression the number of clock cycles in the read pulse phase is gi...

Page 55: ...ccessfully 2 SET the programming voltages by writing the following values otp_mrr 0x4 otp_mpp 0x0 otp_vppen 0x0 3 WAIT 20 us for the programming voltages to stabilize 4 ADDRESS the memory by setting otp_a 5 WRITE one bit at a time a Set only the bit you want to write high in otp_d b Bring otp_ck HIGH for 50 us c Bring otp_ck LOW Note that this means only one bit of otp_d should be high at any time...

Page 56: ...set Stretcher Observe orgenerate AONreset pulse externally aonrst f rst srst erst dw akeup_n LFROSC l f cl k t l cl k PowerManagement Unit pm u_out _0 hf cl kr st cor er st Backup Registers 32 x 32 bit registers Core Voltage Clock Domain m t i p m t i m e VDC aonrst r t ccm pi p m t i p M Real Time Clock rt cm pi p t l l f cl k w dogcm pi p Watchdog w dogrst w dogcm pi p VCDC VAON VCore psdl f al ...

Page 57: ...reset srst The lfroscrst signal is used to initialize the ring oscillator in the LFROSC This oscillator pro vides lfclk which is used to clock the AON lfclk is also used as the clock input to mtime in the CLINT The srst strobe is passed to a reset synchronizer clocked by lfclk to generate aonrst an asychronous onset synchronous release reset signal used to reset most of the AON block The mostly of...

Page 58: ...The Real Time Clock is described in detail in Chapter 15 12 8 Backup Registers The backup registers provide a place to store critical data during sleep The FE310 G000 has 16 32 bit backup registers 12 9 Power Management Unit PMU The power management unit PMU sequences the system power supplies and reset signals when transitioning into and out of sleep mode The PMU also monitors AON signals for wak...

Page 59: ... Register 3 0x090 backup_4 Backup Register 4 0x094 backup_5 Backup Register 5 0x098 backup_6 Backup Register 6 0x09C backup_7 Backup Register 7 0x0A0 backup_8 Backup Register 8 0x0A4 backup_9 Backup Register 9 0x0A8 backup_10 Backup Register 10 0x0AC backup_11 Backup Register 11 0x0B0 backup_12 Backup Register 12 0x0B4 backup_13 Backup Register 13 0x0B8 backup_14 Backup Register 14 0x0BC backup_15...

Page 60: ...leep program instruction 1 0x128 pmusleepi2 Sleep program instruction 2 0x12C pmusleepi3 Sleep program instruction 3 0x130 pmusleepi4 Sleep program instruction 4 0x134 pmusleepi5 Sleep program instruction 5 0x138 pmusleepi6 Sleep program instruction 6 0x13C pmusleepi7 Sleep program instruction 7 0x140 pmuie PMU Interrupt Enables 0x144 pmucause PMU Wakeup Cause 0x148 pmusleep Initiate PMU Sleep Seq...

Page 61: ...r a full power on reset To prevent errant code from resetting the counter the WDT registers can only be updated by presenting a WDT key sequence w dogcm p w dogcf g w dogcm pi p w dogcl k aonrst w dogcount w dogs w dogscal e Wdog TileLink w dogf eed reset w dogrst aonrst en w dogcl k w dogkey corerst Synch w dogzerocm p w dogrst en w dogenal w ays w dogencoreaw ake Figure 6 Watchdog Timer 13 1 Wat...

Page 62: ... 0 wdogscale RW X Counter scale value 7 4 Reserved 8 wdogrsten RW 0x0 Controls whether the comparator output can set the wdogrst bit and hence cause a full reset 9 wdogzerocmp RW X Reset counter to zero after match 11 10 Reserved 12 wdogenalways RW 0x0 Enable Always run continuously 13 wdogcoreawake RW 0x0 Increment the watchdog counter if the processor is not asleep 27 14 Reserved 28 wdogip0 RW X...

Page 63: ...lue in wdogcmp This feature can be used to implement periodic counter interrupts where the period is independent of interrupt service time The wdogrsten bit controls whether the comparator output can set the wdogrst bit and hence cause a full reset The wdogip0 interrupt pending bit can be read or written 13 4 Watchdog Compare Register wdogcmp wdogcmp0 Comparator 0 wdogcmp0 Register Offset 0x20 Bit...

Page 64: ...tchdog Configuration The WDT provides watchdog intervals of up to over 18 hours 65 535 seconds 13 8 Watchdog Resets If the watchdog is not fed before the wdogcount register exceeds the compare register zero while the WDT is enabled a reset pulse is sent to the reset circuitry and the chip will go through a complete power on sequence The WDT will be initalized after a full reset with the wdogrsten ...

Page 65: ...nagement unit PMU is implemented within the AON domain and sequences the system s power supplies and reset signals during power on reset and when tran sitioning the mostly off MOFF block into and out of sleep mode SiFive FE310 G000 Manual v3p2 SiFive Inc Page 62 ...

Page 66: ... wakeup events and sleep requests When the MOFF block is powered off the PMU monitors AON signals to initiate the wakeup sequence When the MOFF block is powered on the PMU awaits sleep requests from the MOFF block which initiate the sleep sequence The PMU is based around a simple pro grammable microcode sequencer that steps through short programs to sequence output signals that control the power s...

Page 67: ...eep program instruction 5 0x138 pmusleepi6 Sleep program instruction 6 0x13C pmusleepi7 Sleep program instruction 7 0x140 pmuie PMU Interrupt Enables 0x144 pmucause PMU Wakeup Cause 0x148 pmusleep Initiate PMU Sleep Sequence 0x14C pmukey PMU Key Reads as 1 when PMU is unlocked 14 3 PMU Key Register pmukey The pmukey register has one bit of state To prevent spurious sleep or PMU program modifica ti...

Page 68: ...registers are all asynchronously set to 1 by aonrst PMU Instruction Format pmu sleep wakeup iX Register Offset 0x100 Bits Field Name Attr Rst Description 3 0 delay RW X delay multiplier 4 pmu_out_0_en RW X Drive PMU Output En 0 High 5 pmu_out_1_en RW X Drive PMU Output En 1 High 7 corerst RW X Core Reset 8 hfclkrst RW X High Frequency Clock Reset At power on reset the PMU program memories are rese...

Page 69: ...tch circuit that requires the dwakeup signal remain asserted for two AON clock edges before being accepted The conditioning circuit also resynchronizes the dwakeup signal to the AON lfclk 14 7 PMU Interrupt Enables pmuie and Wakeup Cause pmucause The pmuie register indicates which events can wake the MOFF block from sleep The dwakeup bit indicates that a logic 0 on the dwakeup_n pin can rouse MOFF...

Page 70: ...rce triggered the wakeup Table 41 lists the values the resetcause field may take The value in resetcause persists until the next reset pmucause PMU Wakeup Cause pmucause Register Offset 0x144 Bits Field Name Attr Rst Description 31 0 pmucause RO X PMU Wakeup Cause Table 40 Wakeup cause values Index Meaning 0 Reset 1 RTC Wakup rtc 2 Digitial input wakeup dwakeup Table 41 Reset cause values Index Me...

Page 71: ...t cscal e Figure 8 Real Time Clock 15 1 RTC Count Registers rtccounthi rtccountlo The real time counter is based around the rtccounthi rtccountlo register pair which incre ment at the low frequency clock rate when the RTC is enabled The rtccountlo register holds the low 32 bits of the RTC while rtccounthi holds the upper 16 bits of the RTC value The total 48 bit counter width ensures there will no...

Page 72: ...ending 31 29 Reserved The rtcenalways bit controls whether the RTC is enabled and is reset on AON reset The 4 bit rtcscale field scales the real time counter value before feeding to the real time inter rupt comparator The value in rtcscale is the bit position within the rtccountlo rtccounthi register pair of the start of a 32 bit field rtcs A value of 0 in rtcscale indicates no scaling and rtcs wo...

Page 73: ...ounter If rtcs is greater than or equal to rtccmp the rtccmpip interrupt pending bit is set The rtccmpip interrupt pending bit is read only The rtccmpip bit can be cleared down by writing a value to rtccmp that is greater than rtcs rtccmp0 Comparator 0 rtccmp0 Register Offset 0x60 Bits Field Name Attr Rst Description 31 0 rtccmp0 RW X Comparator 0 Table 45 rtccmp0 Comparator 0 Chapter 15 Real Time...

Page 74: ...ponsible for low level configuration of actual GPIO pads on the device direction pull up enable and drive value as well as selecting between various sources of the controls for these signals The GPIO controller allows separate configuration of each of ngpio GPIO bits Figure 9 shows the control structure for each pin Atomic operations such as toggles are natively possible with the RISC V A extensio...

Page 75: ...Figure 9 Structure of a single GPIO Pin with Control Registers This structure is repeated for each pin Chapter 16 General Purpose Input Output Controller SiFive FE310 G000 Manual v3p2 SiFive Inc Page 72 ...

Page 76: ...ble 0x0C output_val Output value 0x10 pue Internal pull up enable 0x14 ds Pin drive strength 0x18 rise_ie Rise interrupt enable 0x1C rise_ip Rise interrupt pending 0x20 fall_ie Fall interrupt enable 0x24 fall_ip Fall interrupt pending 0x28 high_ie High interrupt enable 0x2C high_ip High interrupt pending 0x30 low_ie Low interrupt enable 0x34 low_ip Low interrupt pending 0x38 iof_en I O function en...

Page 77: ...sampled by the interrupt logic so the input pulse width must be long enough to be detected by the synchronization logic To enable an interrupt set the corresponding bit in the rise_ie and or fall_ie to 1 If the cor responding bit in rise_ip or fall_ip is set an interrupt pin is raised Once the interrupt is pending it will remain set until a 1 is written to the _ip register at that bit The interrup...

Page 78: ... the software registers port output_en pullup ds input_en may not be used to control the pin directly Rather the pins may be con trolled by hardware driving the IOF Which functionalities are controlled by the IOF and which are controlled by the software registers are fixed in the hardware on a per IOF basis Those that are not controlled by the hardware continue to be controlled by the software reg...

Page 79: ...FO buffers with programmable watermark interrupts 16 Rx oversampling with 2 3 majority voting per bit The UART peripheral does not support hardware flow control or other modem control signals or synchronous serial data transfers 17 2 UART Instances in FE310 G000 FE310 G000 contains two UART instances Their addresses and parameters are shown in Table 48 Table 48 UART Instances Instance Num ber Addr...

Page 80: ... FIFO if the FIFO is able to accept new entries Reading from txdata returns the current value of the full flag and zero in the data field The full flag indicates whether the transmit FIFO is able to accept new entries when set writes to data are ignored A RISC V amoor w instruction can be used to both read the full status and attempt to enqueue data with a non zero return value indicating the char...

Page 81: ...l The txen bit con trols whether the Tx channel is active When cleared transmission of Tx FIFO contents is sup pressed and the txd pin is driven high The nstop field specifies the number of stop bits 0 for one stop bit and 1 for two stop bits The txcnt field specifies the threshold at which the Tx FIFO watermark interrupt triggers The txctrl register is reset to 0 Transmit Control Register txctrl ...

Page 82: ...d write ie register controls which UART interrupts are enabled ie is reset to 0 The txwm condition becomes raised when the number of entries in the transmit FIFO is strictly less than the count specified by the txcnt field of the txctrl register The pending bit is cleared when sufficient entries have been enqueued to exceed the watermark The rxwm condition becomes raised when the number of entries...

Page 83: ...put out of reset given the expected frequency of tlclk Table 56 shows divisors for some common core clock rates and commonly used baud rates Note that the table shows the divide ratios which are one greater than the value stored in the div register Table 56 Common baud rates MIDI 31250 DMX 250000 and required divide values to achieve them with given bus clock frequencies The divide val ues are one...

Page 84: ...0 3333 115211 0 01 384 250000 1536 250000 0 384 1843200 208 1846153 0 16 The receive channel is sampled at 16 the baud rate and a majority vote over 3 neighboring bits is used to determine the received value For this reason the divisor must be 16 for a receive channel Baud Rate Divisor Register div Register Offset 0x18 Bits Field Name Attr Rst Description 15 0 div RW X Baud rate divisor div_width ...

Page 85: ...mapped reads under the assumption that the input clock rate is less than 100 MHz and the external SPI flash device supports the common Win bond Numonyx serial read 0x03 command Sequential accesses are automatically combined into one long read command for higher performance The fctrl register controls switching between the memory mapped and programmed I O modes if applicable While in programmed I O...

Page 86: ...x04 sckmode Serial clock mode 0x08 Reserved 0x0C Reserved 0x10 csid Chip select ID 0x14 csdef Chip select default 0x18 csmode Chip select mode 0x1C Reserved 0x20 Reserved 0x24 Reserved 0x28 delay0 Delay control 0 0x2C delay1 Delay control 1 0x30 Reserved 0x34 Reserved 0x38 Reserved 0x3C Reserved 0x40 fmt Frame format 0x44 Reserved Table 59 Register offsets within the SPI memory map Registers marke...

Page 87: ...ed for generating the serial clock SCK The relationship between the input clock and SCK is given by the following for mula The input clock is the bus clock tlclk The reset value of the div field is 0x3 Serial Clock Divisor Register sckdiv Register Offset 0x0 Bits Field Name Attr Rst Description 11 0 div RW 0x3 Divisor for serial clock div_width bits wide 31 12 Reserved Table 59 Register offsets wi...

Page 88: ...is logical 1 Value Description 0 Data is sampled on the leading edge of SCK and shifted on the trailing edge of SCK 1 Data is shifted on the leading edge of SCK and sampled on the trailing edge of SCK 18 6 Chip Select ID Register csid The csid is a bit register that encodes the index of the CS pin to be toggled by hardware chip select control The reset value is 0x0 Chip Select ID Register csid Reg...

Page 89: ...egister defines the hardware chip select behavior as described in Table 66 The reset value is 0x0 AUTO In HOLD mode the CS pin is deasserted only when one of the fol lowing conditions occur A different value is written to csmode or csid A write to csdef changes the state of the selected pin Direct mapped flash mode is enabled Chip Select Mode Register csmode Register Offset 0x18 Bits Field Name At...

Page 90: ...he deassertion of CS When sckmode pha 1 an additional half period delay is implicit The reset value is 0x1 The intercs field specifies the minimum CS inactive time between deassertion and assertion The reset value is 0x1 The interxfr field specifies the delay between two consecutive frames without deasserting CS This is applicable only when sckmode is HOLD or OFF The reset value is 0x0 Delay Contr...

Page 91: ...onding to proto single dir Tx endian MSB and len 8 For non flash enabled SPI controllers the reset value is 0x0008_0000 corresponding to proto single dir Rx endian MSB and len 8 Frame Format Register fmt Register Offset 0x40 Bits Field Name Attr Rst Description 1 0 proto RW 0x0 SPI protocol 2 endian RW 0x0 SPI endianness 3 dir RW X SPI I O direction This is reset to 1 for flash enabled SPI control...

Page 92: ...contained in the data field For fmt len 8 values should be left aligned when fmt endian MSB and right aligned when fmt endian LSB The full flag indicates whether the transmit FIFO is ready to accept new entries when set writes to txdata are ignored The data field returns 0x0 when read Transmit Data Register txdata Register Offset 0x48 Bits Field Name Attr Rst Description 7 0 data RW 0x0 Transmit d...

Page 93: ...atermark Register txmark The txmark register specifies the threshold at which the Tx FIFO watermark interrupt triggers The reset value is 1 for flash enabled SPI controllers and 0 for non flash enabled SPI con trollers Transmit Watermark Register txmark Register Offset 0x50 Bits Field Name Attr Rst Description 2 0 txmark RW X Transmit watermark The reset value is 1 for flash enabled controllers 0 ...

Page 94: ...ecomes raised when the number of entries in the receive FIFO is strictly greater than the count specified by the rxmark register The pending bit is cleared when suffi cient entries have been dequeued to fall below the watermark See Table 79 SPI Interrupt Enable Register ie Register Offset 0x70 Bits Field Name Attr Rst Description 0 txwm RW 0x0 Transmit watermark enable 1 rxwm RW 0x0 Receive waterm...

Page 95: ...pped memory region is accessed while in SPI flash mode An instruction consists of a command byte followed by a variable number of address bytes dummy cycles padding and data bytes Table 81 describes the function and reset value of each field SPI Flash Instruction Format Register ffmt Register Offset 0x64 Bits Field Name Attr Rst Description 0 cmd_en RW 0x1 Enable sending of command 3 1 addr_len RW...

Page 96: ... 14 Reserved 23 16 cmd_code RW 0x3 Value of command byte 31 24 pad_code RW 0x0 First 8 bits to transmit during dummy cycles Table 81 SPI Flash Instruction Format Register Chapter 18 Serial Peripheral Interface SPI SiFive FE310 G000 Manual v3p2 SiFive Inc Page 93 ...

Page 97: ... of waveforms on output pins pwm gpio and can also be used to generate several forms of internal timer interrupt The comparator results are captured in the pwmcmp ip flops and then fed to the PLIC as potential interrupt sources The pwmcmp ip outputs are further processed by an output ganging stage before being fed to the GPIOs PWM instances can support comparator precisions cmpwidth up to 16 bits ...

Page 98: ...and parameters are shown in Table 82 Table 82 PWM Instances Instance Number Address ncmp cmpwidth 0 0x10015000 4 8 1 0x10025000 4 16 2 0x10035000 4 16 19 3 PWM Memory Map The memory map for the PWM peripheral is shown in Table 83 Chapter 19 Pulse Width Modulator PWM SiFive FE310 G000 Manual v3p2 SiFive Inc Page 95 ...

Page 99: ...ter is held in pwmcount 30 0 and bit 31 of pwmcount returns a zero when read When used for PWM generation the counter is normally incremented at a fixed rate then reset to zero at the end of every PWM cycle The PWM counter is either reset when the scaled counter pwms reaches the value in pwmcmp0 or is simply allowed to wrap around to zero The counter can also be used in one shot mode where it disa...

Page 100: ...run continuously 13 pwmenoneshot RW 0x0 PWM enable one shot run one cycle 15 14 Reserved 16 pwmcmp0center RW X PWM0 Compare Center 17 pwmcmp1center RW X PWM1 Compare Center 18 pwmcmp2center RW X PWM2 Compare Center 19 pwmcmp3center RW X PWM3 Compare Center 23 20 Reserved 24 pwmcmp0gang RW X PWM0 PWM1 Compare Gang 25 pwmcmp1gang RW X PWM1 PWM2 Compare Gang 26 pwmcmp2gang RW X PWM2 PWM3 Compare Gang...

Page 101: ...e is the bit position within the pwmcount register of the start of a cmpwidth bit pwms field A value of 0 in pwmscale indicates no scaling and pwms would then be equal to the low cmpwidth bits of pwmcount The maximum value of 15 in pwmscale corre sponds to dividing the clock rate by 215 so for an input bus clock of 16 MHz the LSB of pwms will increment at 488 3 Hz The pwmzerocmp bit if set causes ...

Page 102: ... 0 pwmcmp1 RW X PWM 1 Compare Value 31 16 Reserved PWM 2 Compare Register pwmcmp2 Register Offset 0x28 Bits Field Name Attr Rst Description 15 0 pwmcmp2 RW X PWM 2 Compare Value 31 16 Reserved PWM 3 Compare Register pwmcmp3 Register Offset 0x2C Table 86 Scaled PWM Count Register Table 87 PWM 0 Compare Register Table 88 PWM 1 Compare Register Table 89 PWM 2 Compare Register Table 90 PWM 3 Compare R...

Page 103: ...mcfg can be set to capture any high output of a PWM comparator in a sticky bit pwmcmp ip for comparator and prevent the output falling again within the same PWM cycle The pwmcmp ip bits are only allowed to change at the start of the next PWM cycle Note The pwmcmp0ip bit will only be high for one cycle when pwmdeglitch and pwmzerocmp are set where pwmcmp0 is used to define the PWM cycle but can be ...

Page 104: ...optionally and individually inverted thereby creating left aligned PWM waveforms high at beginning of cycle 19 10 Generating Center Aligned Phase Correct PWM Waveforms The simple PWM waveforms in Figure 11 shift the phase of the waveform along with the duty cycle A per comparator pwmcmp center bit in pwmcfg allows a single PWM comparator to generate a center aligned symmetric duty cycle as shown i...

Page 105: ...hown for a 3 bit PWM precision The signals can be inverted at the GPIOs to generate opposite phase waveforms When a comparator is operating in center mode the deglitch circuit allows one 0 to 1 transition during the first half of the cycle and one 1 to 0 transition during the second half of the cycle Table 91 Illustration of how count value is inverted before presentation to comparator when pwmcmp...

Page 106: ...will run for one PWM cycle then once a reset condition occurs the pwmenoneshot bit is reset in hardware to prevent a second cycle 19 13 PWM Interrupts The PWM can be configured to provide periodic counter interrupts by enabling auto zeroing of the count register when a comparator 0 fires pwmzerocmp 1 The pwmsticky bit should also be set to ensure interrupts are not forgotten while waiting to run a...

Page 107: ...Debug Control and Status Registers CSR Name Description Allowed Access Modes tselect Trace and debug register select D M tdata1 First field of selected TDR D M tdata2 Second field of selected TDR D M tdata3 Third field of selected TDR D M dcsr Debug control and status register D dpc Debug PC D dscratch Debug scratch register D The dcsr dpc and dscratch registers are only accessible in debug mode w...

Page 108: ... indices of unimplemented TDRs Even if index can hold a TDR index it does not guarantee the TDR exists The type field of tdata1 must be inspected to determine whether the TDR exists 20 1 2 Trace and Debug Data Registers tdata1 3 The tdata1 3 registers are XLEN bit read write registers selected from a larger underlying bank of TDR registers by the tselect register Table 94 tdata1 CSR Trace and Debu...

Page 109: ...information about debug capabilities and status Its detailed functionality is described in The RISC V Debug Specification 0 11 20 1 4 Debug PC dpc When entering debug mode the current PC is copied here When leaving debug mode execu tion resumes at this PC 20 1 5 Debug Scratch dscratch This register is generally reserved for use by Debug ROM in order to save registers needed by the code in Debug RO...

Page 110: ...Rst Description 0 R WARL X Address match on LOAD 1 W WARL X Address match on STORE 2 X WARL X Address match on Instruction FETCH 3 U WARL X Address match on User Mode 4 S WARL X Address match on Supervisor Mode 5 Reserved WPRI X Reserved 6 M WARL X Address match on Machine Mode 10 7 match WARL X Breakpoint Address Match type 11 chain WARL 0 Chain adjacent conditions 17 12 action WARL 0 Breakpoint ...

Page 111: ...f implemented bits must be supported The match field is a 4 bit read write WARL field that encodes the type of address range for breakpoint address matching Three different match settings are currently supported exact NAPOT and arbitrary range A single breakpoint register supports both exact address matches and matches with address ranges that are naturally aligned powers of two NAPOT in size Brea...

Page 112: ...dress Each breakpoint match address register is an XLEN bit read write register used to hold signifi cant address bits for address matching and also the unary encoded address masking informa tion for NAPOT ranges 20 2 3 Breakpoint Execution Breakpoint traps are taken precisely Implementations that emulate misaligned accesses in soft ware will generate a breakpoint trap when either half of the emul...

Page 113: ...ngle bit register as shown below Component Signal Address Register csra Register Offset Bits Field Name Attr Rst Description 1 0 00 RO 0x0 2 value RW X Value to be written 7 3 register RW X Register to be written 31 8 0x000001 RW 0x000001 Component Signal Data Register csrd Register Offset Bits Field Name Attr Rst Description 31 0 component RW X Component select This addressing scheme was adopted ...

Page 114: ... to component 0x108 Clear halt notification from component 0x10C Set halt notification from component 20 3 2 Debug RAM 0x400 0x43f SiFive systems provide at least the minimal required amount of Debug RAM which is 28 bytes for an RV32 system and 64 bytes for an RV64 system 20 3 3 Debug ROM 0x800 0xFFF This ROM region holds the debug routines on SiFive systems The actual total size may vary between ...

Page 115: ...AG interface to test and debug the system The JTAG interface is directly connected to input pins 21 1 JTAG TAPC State Machine The JTAG controller includes the standard TAPC state machine shown in Figure 13 The state machine is clocked with TCK All transitions are labelled with the value on TMS except for the arc showing asynchronous reset when TRST 0 SiFive FE310 G000 Manual v3p2 SiFive Inc Page 1...

Page 116: ...ag_reset signal is synchronized inside the FE310 G000 During operation the JTAG DTM logic can also be reset without jtag_reset by issuing 5 jtag_TCK clock ticks with jtag_TMS asserted This action resets only the JTAG DTM not the debug module 21 3 JTAG Clocking The JTAG logic always operates in its own clock domain clocked by jtag_TCK The JTAG logic is fully static and has no minimum clock frequenc...

Page 117: ...e by connecting the debug scan register between jtag_TDI and jtag_TDO The debug scan register includes a 2 bit opcode field a 5 bit debug module address field and a 34 bit data field to allow various memory mapped read write operations to be specified with a single scan of the debug scan register These are described in The RISC V Debug Specification 0 11 Chapter 21 Debug Interface SiFive FE310 G00...

Page 118: ...n and K Asanovic Eds The RISC V Instruction Set Manual Volume I User Level ISA Version 2 2 May 2017 Online Available https riscv org specifications 2 The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 May 2017 Online Available https riscv org specifications SiFive FE310 G000 Manual v3p2 SiFive Inc Page 115 ...

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