4116922
Rev 1.1
January 21, 2015
46
Hardware Integration Guide
Baseband Specification
Figure 24. I2S Signals Timing Diagram
6.15.2.2.1.
I2S_DIN and I2S_DOUT
The serial PCM stereo-data stream for both channels are output from the AirPrime AR7558 on the
I2S_DOUT signal pin and input on the I2S_DIN signal pin.
Serial data is transmitted in two’s
complement, with the MSB first. The transmitter and receiver are not required to have the same word
length:
When the transmitted word length is greater than the receiver word length, the bits after the
receiver
’s LSB are ignored; the rest of the transmitter’s LSBs are ignored.
When the transmitted word length is less than the receiver word length, the receiver
’s missing
LSB will be set to zero initially, so they will remain at zero.
The MSB has a fixed position, whereas the LSB position depends upon word length.
The transmitter always sends the MSB of the next word one clock period after WS changes.
Serial data sent by the transmitter may be synchronized with either the trailing (H-to-L) or
leading (L-to-H) edge of the clock signal.
Serial data must be latched into the receiver on the leading edge of the serial clock signal.
6.15.2.2.2.
I2S_WS
The word-select line indicates the channel being transmitted / received:
0 specifies the left channel
1 specifies the right channel
The WS signal changes one clock period before the MSB is transmitted.
6.15.2.2.3.
I2S_SCLK
This is the serial bit clock whose rate is a function of the data width and sample rate:
I2S_SCLK rate = (2 x bit_width) x FS
Where bit_width = 16 bits per channel and FS is the sample rate, therefore:
I2S_SCLK rate = 32 x FS
Sample rates of 8, 16, 24, 32, 44.1, and 48 kHz are supported. An example clock rate is:
I2S_SCLK rate = (2 x 16) x 48 kHz = 1.536 MHz
Where bit_width = 16 and FS = 48 kHz.