SIERRA VIDEO SYSTEMS Tahoe 2010A, User Manual

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Sierra Video Systems
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described in the Communication Protocol section of this manual and can be addressed
using the SVS windows program “GRIP”.
Two 8-bit dip switches allow the user to make configuration choices. See the section on
Dip Switch settings.
Power-Up Reset
The power-up reset signal is used to reset the MC68302 under certain conditions. The
primary source of reset is U24, an MC34064 low-voltage detector. This 3 terminal device
detects when the Vcc voltage is below a threshold level and pulls the output to ground.
This condition should arise only when the router is first turned on and the DC voltage
ramps up from the power supply. This signal grounds the enable of ½ of a LS244 bus
driver (12), which simultaneously drives low two outputs which are connected to HALT
and RESET on the MC68302.
The secondary source of reset is the watchdog timer output from the MC68302 itself. If
some internal mechanism of the software fails and the watchdog is not reset periodically,
the watchdog output will pulse low and cause a reset. This signal is also connected to the
enable input of the same LS244.
The software cannot distinguish one form of reset from the other.
Chip Select Decodes
The MC68302 offers 4 chip select decodes. After power-up, the base address and range
of these chip selects can be changed by writing to internal control registers in the
MC68302. Initially, the MC68302 will begin by fetching instructions from the EPROM, and
one of the first things it does is set the range and address of the other chip selects
properly.
The first three chip selects are used by the EPROM (U2), the static RAM (U3) and the
battery RAM (U4). The last chip select is treated specially and described in the next
section.
The EPROM and both RAMs are connected directly to the MC68302’s address and data
bus since it is being used in the 8-bit mode. This is one of the advantages of the
MC68302 as it does not require bus buffers or any additional logic to interface to these
memory parts.
The MC68302 offers selectable DTACK generation and wait state internal on a per-chip
select basis. The 504001 uses internal DTACK and 1 wait state for CSO, CS1, and CS2.
Chip Select 3
Chip select #3 is futher decoded to select whether the memory access is to the LEDs, the
dip switches, or the matrix interface. ½ of an LS139 (U13) is used for this purpose.
Address lines A16 and A17 evenly divide the portion of memory allocated to CS3 into 4
parts.
The two dip switch input enables and the LED latch enable are directly compatible with
the HC541 drivers and HC573 latch; so that these enabling signals go to those parts
directly.
The matrix address and data latches, U5 and U6, however, need to have an enable of
the oppsite polarity to ensure that the data is valid when it is latched. A portion of U15
inverts this signal so that data will be valid when latched.
DTACK Generator
Chip selects 0, 1, and 2 use the internal DTACK generation circuit of the MC68302 and
therefore no special circuitry is needed. (Because of this, an external DTACK signal must
not appear after any of these chip selects are asserted).