Initial Commissioning
SMP16-CPU06x
©Siemens AG 2001, All Rights Reserved
20
(4)J31069-D2085-U001-A2-7618
Function
SMP16-CPU055
SMP16-CPU065
Interrupt matrix for
additional interrupt block
No
Electronic interrupt matrix
R178 Bit 0,1,2
Interrupt enable and
selection
Additional interrupt block No
Controller for various events (outputs of
additional counters, DREQ signals of the
SMP16 bus)
R130/131
Registers of the extra
8259 (ICW, OCW)
R133 read
INTA add. 8259
Cascaded interrupts on
the SMP16 bus
No
Starting with KS02:
Additional interrupt controller on SMP16 bus
can be cascaded.
R178
Bit 3
Enable CAS_EN
Buffered SRAM
No
Maximum of 128 kbytes
R17A
Base address
R17D Bit 5, 6, 7
Enable and length
of the window.
Digital inputs/outputs,
TTL level
No
Starting with KS02:
wo 8-bit ports can be parameterized as input
or output.
R138/9
Data ports
R13A
Control regis ter
Port 0 can also be set as clock pulse and gate
inputs of the additional counter.
R13C
Parameterization
Serial EEPROM
Access via GPP2 of the FDC37C932
(0EAh/0EBh bits 0 to 2: DI, DO,
CLK)
Access via GPP2 of the PIIX4E
R4035 Bit 2:
Clock pulse for ser.
EEPROM
(GPO10)
R4035 Bit 1
Data for ser. EEPROM
(GPO9)
R4032 Bit 1
Data from ser. EEPROM
(GPI17)
USER LED
Two LEDs can be addressed via
GPIO of the FDC37C932, can be
used (via jumper) for the hard disk
channels to indicate access.
Four LEDs can be used for on-board
indications (via BIOS Setup or SW).
R17C
Bit 0-3
Default USER
USER LED can be address via GPO of
PIIX4E.
R4034 Bit 0
LED 0 (GPO0)
R4035 Bit 1
LED 1 (GPO8)
R4037 Bit 3
LED 2 (GPO27)
R4037 Bit 4
LED 3 (GPO28)
SMP_INT
Fixed on IRQ15
For PC compatibility's sake, IRQ15 is
permanently assigned to the secondary EIDE
channel.
SMP_INT can only be fed in with one of the
SMP_IRQs.
Starting with KS02:
Depending on the EIDE channel
SMP_INT is assigned to
IRQ14 or IRQ15 (or neither of the two).
