Siemens ERTEC EB 200, Manual

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2 Hardware Structure of the EB 200
2.1 ERTEC 200
2.1.1 Function Overview
Refer to documents /1/ and /2/ for a detailed function description of the ERTEC 200.
In this manual, only the main components are described briefly and represented in a block diagram.
The following four AHB masters are integrated in the ERTEC 200:

ARM946E-S with trace/debug port and high-performance interrupt controllers

IRT switch with 64 Kbytes of K-RAM for real-time Ethernet communication

External host processor on the LBU interface

Single channel DMA controller
The following I/O blocks are available to the masters:

External memory interface (EMIF) with SDRAM and SRAM controller

Two Ethernet interfaces with integrated MII PHYs

I/O via APB bridge

45-bit GPIO
 UART
 SPI
 3 timers
 F-timer
 Watchdog
 Boot ROM
 System function register
The multi-layer AHB bus system enables a largely independent operation of the masters. An internal arbitration logic
prevents access conflicts if multiple masters want to access the same I/O block. The function groups of the ERTEC
200 are shown in the following block diagram:
D M A -
C o n tro lle r
A H B /A P B
B rid g e
G P IO
Mas
ter
M a s te r
P
P
o
r
t
s
7
A P B
5 0 M H z / 3 2 B it
7 4
L B U / M II + S M I /
E T M / G P IO
1 x U A R T
S P I1
In te rfa c e
3 x T im e r ,
W a tc h d o g ,
F - T im e r
AR
M9
cl
ock
50
M
H
z
100MHz
1 1
2 5 M H z
S C - B u s (5 0 M H z )
3 2 B it
2 -P o rt S w itc h
S w itc h C o n tro l
K -S R A M
6 4 k B y te
E th e rn e t-
K a n a l
(P o rt 0 )
E th e rn e t-
K a n a l
( P o r t 1 )
2 1
2 0
3 2
5
G P IO ,
U A R T ,
S P I,
T im e r ,
W a tc h d o g ,
P H Y 0
A H B -
W r a p p e r
S la v e
M a s te r
Sl
ave
Sl
ave 2
Sl
av
e
B o o t-
R O M
( 8 k B y te )
Sl
av
e
3 2
8
1
T e s t
M u lti-L a y e r-A H B
5 0 M H z /3 2 B it
M e m o ry -
C o n tro lle r
(E M IF )
S la v e
In p u t
s ta g e
M U X /A r b .
M U X /A rb .
MU
X/
Ar
b.
4
R e s e t
S y s te m
C o n tro l
C lo c k - U n it
F _ C L K
4 8
L o c a l
B u s U n it
1 6 B it
(L B U )
M a s te r
In p u t
s ta g e
M U X
E R T E C 2 0 0
M C - P L L S ig n a ls
P H Y
( P o r t 0 )
P H Y
(P o r t 1 )
A R M 9 4 6 E S
w ith
I-C a c h e
(8 k B y te )
,
D -C a c h e
(4 k B y te )
,
D -T C M
(4 k B y te )
M a s te r
7
B S -
T A P
J T A G / D e b u g
A H B -
W ra p p e r
M a s te r
M C -B u s (5 0 M H z )
3 2 B it
S la v e
In p u t
s ta g e
A R M -
In te rru p t-
C o n tro lle r
S la v e
D e c o d e
In p u t
s ta g e
S la v e
D e c o d e
1
M II- 0
M II-1
P L L
4 8
S M I
3
1 6
1 6
E x te r n a l
M e m o ry In te rfa c e
P H Y 1
1
R E F _
C L K
E T M
In te rfa c e
T R A C E _
C L K
1 4
1
1 3
1 3
Sl
av
e
Sla
ve
Sla
ve
Figure 2: ERTEC 200 Block Diagram
Copyright © Siemens AG 2010. All rights reserved.
11
EB 200 Manual
Technical data subject to change Version 1.1.4