SICK HIPERFACE DSL, Technical Information

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9 FPGA IP-Core
The HIPERFACE DSL
®
interface is installed in the frequency inverter system via a special
protocol logic circuit, known as the DSL Master. The circuit is installed in an FPGA com‐
ponent and is supplied as an Intellectual Property Core (IP Core). The IP Core of the DSL
master is supplied in a form such that it can be freely connected within the FPGA. If
there is sufficient space within the FPGA used, the DSL Master can be installed in the
same component as the frequency inverter application.
To be able to join different components to the IP Core, e.g. internal FPGA buses, various
open-source interface blocks are supplied with the IP Core.
figure 34 shows the block circuit diagram of the DSL Master circuit without the inter‐
face blocks. Signal characteristics are listed in table 184 , functional characteristics in
table 185 .
DSL Core top level Safety variant only
parameter
RX
CRC checker
interrupt
controller
main
function
registers
secondary
registers
SYNC
DSL OUT
DSL enable
Protocol
Manager 2
Safe 2 Interface
interrupt Events
SPI PIPE
CRC checker
Safe 1 interface
pipeline
CRC checker
integrator
+
estimator
DSL IN
parameter
TX
sync
generator
framer
sampler
sequencer
protocol
manager
fast_pos_rdy
safe_pos_err
estimator_on
safe_channel_err
dev_thr_err
2)
3)
Drive interface
2) Optional interface, SPI only
3) Interface only available in Safety variant
Figure 34: Block circuit diagram of the DSL Master IP Core
Table 184: Signal characteristics of the DSL Master IP Core
Signal characteristics
IP Core clock – "clk"
Frequency 75.0 MHz
Frequency tolerance ±100 ppm
IP Core reset – "rst" High active
Minimum reset duration after switch on/loading 20 ns
HIPERFACE DSL ® interface
9
FPGA IP-CORE
136 T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
8017595/ZTW6/2018-01-15 | SICK
Subject to change without notice