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DRAM Timing
Set this to the default value to enable the system to automatically set the
SDRAM timing by SPD (Serial Presence Detect). SPD is an EEPROM
chip on the DIMM module that stores information about the memory
chips it contains, including size, speed, voltage, row and column
addresses, and manufacturer. If you disable this item, you can use the
following three items to manually set the timing parameters for the
system memory
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The Choice: Manual or By SPD.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. We recommend that you
leave this item at the default value.
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The Choice: 3, 2.5, or 2.
Bank Interleave
The interleave number of internal banks, can be set to 2 way, 4 way
interleave or disabled. For VCM and 16Mb type dram chips, the bank
interleave is fixed at 2 way interleave.
When the dram timing is selected by SPD, it will be set by the value on
SPD of the RAM module(SDR).
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The Choice: Disabled, 2 Bank, or 4 Bank.
DRAM Command Rate
This item enables you to specify the waiting time for the CPU to issue
the next command after issuing the command to the DDR memory. We
recommend that you leave this item at the default value.
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The Choice: 2T Command or 1T Command.
AGP & P2P Bridge Control
Options are in its sub-menu.
Press <Enter> to enter the sub-menu of detailed options.
AGP Aperture Size (MB)
Select the size of Accelerated Graphics Port (AGP) aperture. The aper-
ture is a portion of the PCI memory address range dedicated to graphics
memory address space. Host cycles that hit the aperture range are
forwarded to the AGP without any translation.
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The Choice: 4M, 8M, 16M, 32M, 64M, 128M, or 256M.
