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AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By
default, two-wait states are used by the system, allowing for greater
stability.
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The Choice: Disabled or Enabled.
CPU & PCI Bus Control
Press <Enter> to enter the sub-menu of detailed options.
CPU to PCI Write Buffer
When enabled, writes from the CPU to PCU bus are buffered, to compen-
sate for the speed differences between the CPU and PCI bus. When dis-
abled, the writes are not buffered and the CPU must wait until the write is
complete be-fore starting another write cycle.
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The Choice: Disabled or Enabled.
PCI Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero wait states.
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The Choice: Disabled or Enabled.
PCI Delay Transaction
The mainboard’s chipset has an embedded 32-bit post write buffer to sup-
port delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The Choice: Disabled or Enabled.
System BIOS Cacheable
This item allows the system to be cached in memory for faster execu-
tion. Leave these items at the default value for better performance.
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The choice: Disabled or Enabled.
VGA Share Memory Size
This item enables you to specify the system memory size to allocate to
the video memory.
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The choice: Disabled or Enabled.
Init Display First
Use this item to define if your graphics adapter is installed in one of the
PCI slots or select onboard if you have a graphics system integrated on
the moth-erboard.
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The choice: PCI Slot or AGP.
