30
CPU to PCI Write Buffer
When enabled, up to four words of data can be written to the PCI bus without interrupting the CPU.
When disabled, a write buffer is not used and the CPU read cycle will not be completed until the
PCI bus signals that it is ready to receive the data..
The choice: Enabled, Disabled.
PCI Dynamic Bursting
When Enabled, data transfers on the PCI bus, where possible, make use of the high-performance
PCI bust protocol, in which greater amounts of data are transferred at a single command..
The choice: Enabled, Disabled.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are command with zero wait states.
The choice: Enabled, Disabled.
PCI IRQ Activated by
This item sets the method by which the PCI bus recognize that an IRQ service is being requested by
a device. You should never change the default configuration unless advised otherwise by your
System’s manufacturer. Choices are
Level
(default) and
Edge
.
PCI IDE IRQ Map to
This items allows you to configure your system to the type of IDE disk controller in use. By
default, Setup assumes that your controller is an ISA device rather than a PCI controller.
If you have equipped your system with a PCI controller, changing this allows you to specify which
slot has the controller and which PCI interrupt (A, B, C or D) is associated with the connected hard
drives.
Remember that this setting refers to the hard disk drive itself, rather than individual partitions.
Since each IDE controller supports two separate hard disk drives, you can select the INT# for each.
Again, you will note that the primary has a lower interrupt than the secondary as described in
“Slot x Using INT#”
above.
Selecting
“PCI Auto”
allows the system to automatically determine how your IDE disk system is
configured.
MS IRQ Routing Table
This item allows the user to set BIOS IRQ Routing table Enabled or Disabled.
ACPI I/O Device Node
This item allows the user to set ACPI I/O Device Node Enabled or Disabled.
