Shuttle HOT-559 User Manual Download Page 13

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User's Manual 13

CPU Freq. (MHz)

JP12

Host Bus

Freq. (MHz)

JP27

JP14

JP15

CPU Clock

Multiplier

Pin
1-2

Pin
3-4

Pin
5-6

Cyrix 6x86L

PR166

Open

Pin 2-3 Close

Pin 1-2 Close

x 2

Cyrix 6x86

PR166

Open

Pin 2-3 Close

Pin 1-2 Close

x 2

Cyrix 6x86L

PR150

Open

Pin 2-3 Close

Pin 1-2 Close

x 2

Cyrix 6x86

PR150

Open

Pin 2-3 Close]

Pin 2-3 Close

Pin 1-2 Close

x 2

Cyrix 6x86

PR133

Open

Pin 2-3 Close

Pin 1-2 Close

x 2

Cyrix 6x86

PR120

Pin 2-3 Close

Pin 1-2 Close

x 2

2.3 Onbaord Regulator Output- JP24, JP25

HOT-559(S) main board is designed with an advanced onboard switching voltage
regulators to provide 3.3V ~3.52V range voltage (V

CORE

) for intel Pentium

P54C, Cyrix 6x86 and AMD K5 processors; and also provide dual 3.3/2.8V~
3.3/3.2V ranges voltage (V

, V

CORE

separated) for Intel Pentium P55C, Cyrix/IBM

6x86L and AMD K6 processors. Single or dual voltages output according to the
following tables.

Processors

Vcore

JP24

JP25

Pentium MMX

150~233 MHz

2.8 V

Pin 5-6 Close

Pin 1-3, 2-4 Close

AMD K-6

PR2-166/200

2.9 V

Pin 1-2, 5-6 Close

AMD K-6

PR2-233/266

3.2 V

Pin 3-4 Close

Cyrix 6x86L

PR150/166

2.8 V

Pin 5-6 Close

Processors

Vcore

JP24

JP25

Pentium

75~200 MHz

3.3 V

Pin 3-4, 5-6 Close

Pin 3-5, 4-6 Close

AMD K-5

PR75~166

3.52 V

Pin 1-3, 5-6 Close

Cyrix 6x86

PR120~166(3.3V)

3.3 V

Pin 3-4, 5-6 Close

Cyrix 6x86

PR120~166

3.52 V

Pin 1-3, 5-6 Close

Summary of Contents for HOT-559

Page 1: ...rence Problems This booklet is available from the U S Government Printing Office Washington DC 20402 Stock 004 000 00345 4 FCC Warning The user is cautioned that changes or modifications not expressly approved by the manufacturer could void the user s authority to operate this equipment Note In order for an installation of this product to maintain compliance with the limits for a Class B device sh...

Page 2: ...ectors 10 2 JUMPER SETTINGS 11 2 1 Jumper Block Overview 11 2 2 CPU Configuration JP12 JP14 JP15 and JP27 12 2 3 Onboard Regulator Output JP24 JP25 13 2 4 Other Jumpers Setting 14 3 BIOS AND SETUP UTILITY 15 3 1 Introduction 15 3 2 BIOS Upgrades 15 3 3 Entering Setup 15 3 4 The Main Menu 16 3 5 Standard CMOS Setup 18 3 6 BIOS Feature Setup 20 3 7 Chipset Features Setup 22 3 8 Power Management Setu...

Page 3: ...es include Supports 8MB to 128 MB of Synchronous DRAM EDO DRAM or standard Fast Page DRAM in 72 pin SIMM and 168 pin DIMM sockets Type 7 Pentium OverDrive socket provides an upgrade to future OverDrive Cyrix 6x86 6x86L and AMD K5 K6 processors Intel s 82430VX PCIset ITE 8680 Giga I O controller Bus mastering IDE Supports pipeline burst cache with size of 512KB or 256KB Onboard Adaptec AIC 7880 16 ...

Page 4: ...4 User s Manual 1 1 1 HOT 559S Layout ...

Page 5: ...User s Manual 5 1 1 2 HOT 559 Layout ...

Page 6: ...2 233 and PR2 266 are supported 1 4 Memory Second level Cache The Intel 82430VX Xcelerated Controller PCIset supports 512KB or 256KB second level cache that uses the Synchronous Pipeline Burst SRAM Pipeline Burst PB SRAM provides performance similar to Synchronous Burst SRAMs for only a slight cost premium over slower performing Asynchronous SRAMs Main System Memory The HOT 559 mainboard provides ...

Page 7: ...hannel interrupt controllers PCI to AT interrupt mapping circuitry NMI logic ISA refresh address generation and PCI ISA bus arbitration circuitry together onto the same device The PIIX3 comes in a 208 pin QFP package IDE Support The HOT 559 S main board provides two independent high performance bus mastering PCI IDE interfaces capable of supporting PIO Mode 3 and Mode 4 devices The system BIOS sup...

Page 8: ...drive is incorporated into a single component the ITE 8680F This component provides Two 16C550 compatible UARTs with send receive 16 byte FIFO Support for an Infra Red interface Multimode bidirectional parallel port Standard mode IBM and Centronics compatible Enhanced Parallel Port EPP with BIOS Driver support High Speed mode Extended Capabilities Port ECP compatible Industry standard floppy contr...

Page 9: ...ard hot key or prolonged system inactivity The Sleep Resume button is supported by a 2 pin header located on the front panel I O connector Closing the Sleep switch will generate an SMI System Management Interrupt to the processor which immediately goes into System Management Mode SMM the so called Sleep mode The front panel Sleep mode switch must be a momentary two pin SPST type that is normally o...

Page 10: ...the system will hard reset and run POST Back Panel Connectors The back panel provides external access to PS 2 style keyboard and mouse connec tors as well as two serial and one parallel port which are integrated on the HOT 559 main board please refer to diagram on next page USB Connectors The main board provides two sets USB Universal Serial Bus connectors J27 and J29 for USB devices use 1 9 Add i...

Page 11: ... it possible to change the system configuration The system has been properly configured at the factory Normally the only time you will ever change a jumper is if you need to Change the processor operating speed system bus clock x multiplier Change the system regulator voltage output for the processor requiring Clear CMOS Data ...

Page 12: ... 1 5 AMD K 5 PR100 Close Open Close 66 Pin 2 3 Close Pin 2 3 Close Pin 2 3 Close x 1 5 AMD K 5 PR90 Open Close Close 60 Pin 2 3 Close Pin 2 3 Close Pin 2 3 Close x 1 5 AMD K 5 PR75 Close Close Close 50 Pin 2 3 Close Pin 2 3 Close Pin 2 3 Close x 1 5 CPU Freq MHz JP12 Host Bus Freq MHz JP27 JP14 JP15 CPU Clock Multiplier Pin 1 2 Pin 3 4 Pin 5 6 Pentium MMX 233 MHz Close Open Close 66 Pin 2 3 Close ...

Page 13: ...t JP24 JP25 HOT 559 S main board is designed with an advanced onboard switching voltage regulators to provide 3 3V 3 52V range voltage V IO VCORE for intel Pentium P54C Cyrix 6x86 and AMD K5 processors and also provide dual 3 3 2 8V 3 3 3 2V ranges voltage VIO VCORE separated for Intel Pentium P55C Cyrix IBM 6x86L and AMD K6 processors Single or dual voltages output according to the following tabl...

Page 14: ...e CMOS memory retains the system configuration information in the component of R T C You should move the jumper cap from pin 1 2 to Pin 2 3 of JP4 for a brief moment when you wish to clear CMOS memory and then make sure remove the jumper cap back to pin 1 2 for normal operation to retain your new CMOS data Flash EEPROM Vpp JP1 HOT 559 S mainboard supports two types of flash EEPROM 5 volt and 12 vo...

Page 15: ...virtual mode Memorymanager like QEMM386 EMM386 should not be loaded or Simply bypass all config sys and autoexec bat 3 3 Entering Setup HOT 559 BIOS ROM has a built in Setup program that allows users to modify the basic system configuration This type of information is stored in battery backed RAM so that it retains the Setup information when the power is turned off Power on the computer and press ...

Page 16: ...all the items of Power Management features PCI Configuration setup This item specifies the value in units of PCI bus blocks of the latency timer for the PCI bus master and the IRQ level for PCI device Power on with BIOS defaults Load BIOS Defaults BIOS defaults loads the values required by the system for the maximum performance However you may change the parameter through each Setup Menu Load Setu...

Page 17: ...Supervisor Password Change set or disable supervisor password It allows you to limit access to the system and Setup or just to Setup User Password Change set or disable user password It allows you to limit access to the system and Setup or just to Setup Save Exit setup Save CMOS value change to CMOS and exit setup Exit without saving Abandon all CMOS value changes and exit setup ...

Page 18: ...er Note that the specifications of your drive must match with the drive table The hard disk will not work properly if you enter improper information for this item If your hard disk drive type is not matched or listed you can use Type User to define your own drive type manually If you select Type User related information is asked to be entered to the following items Enter the information directly f...

Page 19: ...m will stop when an error is detected during power up Memory This item is display only It is automatically detected by POST Power On Self Test of the BIOS Base Memory The POST of the BIOS will determine the amount of base or conventional memory installed in the system The value of the base memory is typically 512K for systems with 512K memory installed on the mainboard or 640K for systems with 640...

Page 20: ...uter searches first for the disk operating system The system supports feature of boot from IDE D E or F drive if there are present boot from CD ROM and boot from SCSI drive Default value is A C SCSI Swap Floppy Drive When this item enables the BIOS will swap floppy drive assignments so that Drive A will function as Drive B and Drive B as Drive A Boot Up Floppy Seek During POST BIOS will determine ...

Page 21: ...ws you to select the delay between when the key was first depressed and when the acceleration begins Security Option This item allows you to limit access to the system and Setup or just to Setup When System is selected the system will not boot and access to Setup will be denied if the correct password is not entered at the prompt When Setup is selected the system will boot but access to Setup will...

Page 22: ...charge Time DRAM must continually be refreshed or it will lose its data Normally DRAM is refreshed entirely as the result of a single request This option allows you to determine the number of CPU clocks allocated for Row Address Strobe to accumulate its charge before the DRAM is refreshed If insufficient time is allowed refresh may be incomplete and data lost This item sets the DRAM RAS Precharge ...

Page 23: ...ry Address to RAS Delay which control DRAM Row Miss timings Fast EDO Path Select This item is used to defined fast path is selected for CPU to DRAM read cycles for the leadoff the options are Enable or Disable Refresh RAS Assertion This item is used to set the number of clocks RAS is asserted for Refresh cycles SDRAM CAS Lat RAS to CAS This item is used to set CAS Latency and RAS to CAS clock for ...

Page 24: ... NA 1 to 4 CPU clocks Memory Hole At 15M 16M In order to improve performance certain space in memory can be reserved for ISA cards This memory must be mapped into the memory space below 16 MB Peer Concurrency Peer concurrency means that more than one PCI device can be active at a time Enabled this item allows multiple PCI devices can be active Passive Release When enabled the chipset provides a pr...

Page 25: ... timer values are used such that all timers minimum value PM Control by APM If this item set to No system BIOS will ignore and APM calls when the power is managed the system If this item setup to Yes system BIOS will wait for APM s prompt before it enter any PM mode e g DOZE STANDBY or SUSPEND Video Off Method Blank Screen The system BIOS will only blanks off the screen when disabling video V H SY...

Page 26: ...e turn off IRQ3 5 8 12 Wake Up Events In Doze Standby If these items set to Off the IRQ3 5 8 or 12 event s activity will not reactivates the system from Doze and Standby mode If these items set to On the IRQ3 5 8 or 12 event s activity will reactivate system from Doze and Standby mode Power Down Resume Events If this items sets to Off the event s activity will not be monitored to entering power ma...

Page 27: ...es However this capability means absolutely nothing unless you are using a Plug and Play operating system as Windows 95 Reset Configuration Data This item allows you to determine reset the configuration data or not IRQ 3 4 5 7 9 10 11 12 14 15 assigned to These items allow you to determine the IRQ assigned to the ISA bus and is not available to any PCI slot Choices are Legacy ISA and PCI ISA PnP D...

Page 28: ... is an ISA device rather than a PCI controller If you have equipped your system with a PCI controller changing this allows you to specify which slot has the controller and which PCI interrupt A B C or D is associated with the connected hard drives Remember that this setting refers to the hard disk drive itself rather than individual partitions Since each IDE controller supports two separate hard d...

Page 29: ...gs for on board Primary Master PIO timing IDE Primary Slave PIO In this items there are five modes defined in manual mode and one automatic mode There are 0 1 2 3 4 and AUTO is the default settings for on board Primary Slave PIO timing IDE Secondary Master PIO In this items there are five modes defined in manual mode and one automatic mode There are 0 1 2 3 4 and AUTO is the default settings for o...

Page 30: ...C Control This item specifies onboard floppy disk drive controller This setting allows you to connect your floppy disk drives to the onboard floppy connector Choose the Dis abled settings if you have a separate control card Onboard Serial 1 This item is used to define onboard serial port 1 to3F8 IRQ4 2F8 IRQ3 3E8 IRQ4 2E8 IRQ3 Auto or Disabled Onboard Serial 2 This item is used to define onboard s...

Page 31: ... The options areSPP Standard Parallel Port EPP Enhanced Parallel Port ECP Extended Capabilities Port and EPP ECP ECP Mode Use DMA This item specifies DMA Direct Memory Access channel when ECP device is in use The options are DMA 1 and DMA 3 This item will not show up when SPP and EPP ...

Page 32: ...e asked to confirm the password Type the password again and press Enter You may also press Esc to abort the selection and not enter a password To disable password just press Enter when you are prompted to enter password A message will confirm the password being disabled Once the password is disabled the system will boot and you can enter Setup freely Password Disable If you select System at Securi...

Page 33: ...HOT 559 Pentium Processor Based PCI MAIN BOARD User s Manual ...

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