Shure U4D, Service Manual

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Shure U4D Dual Diversity UHF Receiver
2
25D1062 (AG)
Circuit Description
Circuit Description
Power Section
The receiver accepts power line voltage ranging from 85 Vac to 264
Vac. The receiver hardware uses the +5 Vdc, +12 Vdc and 12 Vdc volt-
ages from the switching power supply. The switching power supply has
40 W overall output power capability, with maximum current capabilities
of 4A at 5V, 2A at +12V, and .5A at –12V. It also includes a fast–acting
2.5A fuse.
Up to four in-line rf amplifiers may be connected to the receiver,
depending on system setup. The receiver provides dc power to the in-
line amplifiers via the BNC antenna ports and RG58 cables. Maximum
dc power supplied to each antenna port is limited by self–resettable fuse.
Rf Section
The rf circuit description is limited to one rf strip (channel A) in
receiver 1. The other rf strip (channel B) is virtually identical. The local
oscillator (LO) section is common for both channels and is described
separately. Receiver 2 is identical to receiver 1.
The rf input signals are sent from the antenna ports to the receiver
via cables with BNC and rf mini–plug connectors. Antenna port A is con-
nected to J302 of receiver 1. Antenna port B is connected to J302 of
receiver 2. Connectors J302 on each receiver are the input of the rf
power dividers.
Each of these splits the rf power from the antenna between two
receivers. The outputs of the power dividers are connected to the inputs
of the opposite rf strips of the other receiver: J303 of receiver 1 to J304
of receiver 2; and J303 of receiver 2 to J304 of receiver 1. In addition,
J306 on receiver 1 and J306 on receiver 2 have to be solder jumpered to
provide connection from the outputs of the rf power dividers to channel A
rf strips of both receivers.
Rf Channel
The rf signal is preselected to the appropriate frequency range with
two dielectric filters. The first dielectric filter is located between the
antenna port and the low noise amplifier (LNA). The second filter is
located between the LNA block and mixer input. The front end down–
converter integrated circuit contains the LNA block and the first mixer.
The first conversion produces the first intermediate frequency (IF)
signal at 50 MHz. The first if signal is amplified with the MMIC, band-
limited with a SAW filter, then down-converted to the second IF frequen-
cy (10.7 MHz) with a second down-converter.
The second down-converter has an internal second local oscillator
(LO) that oscillates at 60.7 MHz, using an external crystal. The second
LO buffered output also provides the LO drive to channel B of the sec-