Sharp PZ-43MR2U, Service Manual

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PZ-MR2T
PZ-43MR2U
PZ-50MR2U
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45, 64, 100
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Pin Function
Pin No. Pin Name I/O Pin Function
DGND
DVDD
MRAS
MA8
MA7-MA0
MCAS
MWE
MOE
MIO15-MIO0
DGND
XI
XO
DVDD
HO3-HO0
HWCK
HRCK
HRST
HI3-HI0
AVDD
FSCO
AGND
AGND
FSCI
CPLL
RPLL
AVDD
CKMD
CLK8
RSTB
SLA0
SCL
SDA
ST0
ST1
NSTD
DYCO0-DYCO9
ALTF
CSI
TEST
LINE
KIL
AVDD
CBPC
ACO
AYO
CBPY
AGND
AGND
AYI
VCLY
VRBY
VRTY
AVDD
AVDD
VRTC
VRBC
ACI
AGND
—
—
O
O
O
O
O
O
I/O
—
I
O
—
O
O
O
O
I
—
—
—
—
—
—
I
—
I
O/I
I
I
I
I/O
O
O
O
I/O
O
I
I
I
I
—
O
O
O
O
—
—
I
O
O
O
—
—
O
O
I
—
Digital section grounding.
Digital section power.
External EDO memory RAS output.
External EDO memory address output.
External EDO memory address output.
External EDO memory CAS output.
External EDO memory WE output.
External EDO memory OE output.
External EDO memory data input/output.
fsc generator digital section grounding.
fsc generator reference clock input.
fsc generator reference clock reverse output.
fsc generator digital section power.
External field memory data output.
External field memory write clock output.
External field memory read clock output.
External field memory reset signal output.
External field memory input.
fsc generator DAC power.
fsc generator fsc output.
fsc generator DAC grounding.
8fsc-PLL grounding.
8fsc-PLL fsc input.
8fsc-PLL filter output.
Test input.
8fsc-PLL power.
CLK8 test mode select (L: Usual, H: Test mode).
8fsc clock output (8fsc clock input at CLK8 test mode).
System reset input (Active Low).
(Active-Low reset pulse input from outside)
PC bus slave address select input (L: B8/B9h, H: BA/BBh).
PC bus clock input (To be connected to system’s SCL line).
PC bus clock input/output (To be connected to system’s SDA line).
nternal signal monitor output.
Internal signal monitor output.
Non-standard detection monitor output.
(L: Judged standard, H: Judged non-standard)
EXADINS=0: Digital Y/C signal alternate output.
EXADINS=1: External Y-ADC data input.
(Non-used lower bits to be connected to GND with resistor in between)
EXADINS=0: Digital Y/C signal alternate flag output (L: Y, H: C).
EXADINS=1: External Y-ADC 4fsc clock output.
Composite sync input (Active Low).
IC select test terminal (L: Usual operation, H: Test mode). (Connected to GND)
Forced line-to-line process select input (L: Usual operation, H: Forced line-to-line
processing).
External killer input (L: Usual operation, H: Forced Y/C separation stop).
Y-DAC, C-DAC power.
C-DAC phase compensation output.
C-DAC analog C signal output.
Y-DAC analog Y signal output.
Y-DAC phase compensation output.
Y-DAC, C-DAC grounding.
Y-ADC grounding.
Y-ADC analog composite signal/Y signal input.
Y-ADC clamp potential output.
Y-ADC bottom reference voltage output.
Y-ADC top reference voltage output.
Y-ADC power.
C-ADC power.
C-ADC top reference voltage output.
C-ADC bottom reference voltage output.
C-ADC analog C signal input.
C-ADC grounding.