Sharp MZ-5500 Tehnical Manual Download

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Summary of Contents for MZ-5500

Page 1: ...MZ 5500 5600 TECllNICAL REFERENCE Vol 2 HARDWARE SlIARP CORPORATION ...

Page 2: ...eries hardware description 2 1 2 MZ 5600 series hardware description r 3 1 3 MZ 5500 specification 1 4 MZ 5600 specification b 1 5 Optional devices specificationß for MZ 5500 5600 g 1 6 Optional devices specifications for MZ 5500 0 1 7 Optional devices specificatio s for MZ 5600 10 ...

Page 3: ...l dis kin t e r fa ce gene r a L des c r i p t ion 55 Print e r interface g 9 I Circ lIit description 9 2 lI 1ndling printer control code function code 60 9 3 M 1king a hard copy of tlle video screen 60 10 RS 2J2C interface bl 1 I Spec ification 6 10 2 Input output si nals and control signals 62 lO J Pro ce S s ou t 1i ne 64 10 4 Wiring e xample 66 I 5 RS2J2C sample program 6 1I Kp yboard and keyb...

Page 4: ...e following external me ory expansion and higher processing speed 1 8MHz 5MHz selective for operation of the 8086 11 epu 2 Implementation of the 640KB form tted 5 2511 floppy disk drive 3 Use of the 10 7MB formatted 5 25 hard disk MZ s64s Not only the MZ s645 has one unit of the internal llard disk drive it also enhances expansion to 21 4MB when the MZ IF18 external hard disk drive is added applic...

Page 5: ...c logicaIOD processor M21M03 8087 I MZ1F02 MZ1K07 10 Fig 1 Specifications System highlights Model description 1 High data processing capability achieved wilh a 16 bit microprocessor 2 Large addr essable memory space of 512 KB Standard 255KB plus an additional 256KB 3 High resolution color graphie display with large capacity video screen memory and bit map display 4 One or two mini floppy disk driv...

Page 6: ...h data processing capability achieved with a 16 bit microprocessor 2 Large addressable memory space of 5 12 Kß Standard 256KB plus an additional 2 6KB 3 High resolution color graphie display with large capacity video screen memory and bit map display 4 One or two mini floppy disk drives each of 640KB are provided as a standard feature And the MZ5645 is 10 7MB Hard disk is standard 5 Powerful stand...

Page 7: ... 400 640 x 200 320 x 200 2 4 B Color 8 colors lean be specified for each dot Granat Ion B gradat ions available with the dedicated monitor Available on a monochrome monitor J 013 wilh a 640 x 400 matrix SCI een char acter confIguration Display capacity Character fell 40 or 80 characters on each row The number of rOw5 per sereen is progr ammable 8 x B 8 x 16 Controlled by software Screen control Su...

Page 8: ... AAM PWB OP 1 0 I F Hard dlsk dr ive I F PWB Expansion Unit Op Opt MZ 1Ett SFD I F PWB Opt SFP I F PWB Avallable with the MZ IX 10 Attached to keyboard device Opl Mouse Additional Additional drive to be installed in Available wilh the MZ IF oq incremenl Single drive Opt MFO For MZ5511 only MFO unit the Synem Unit ÄVililable with the MZ 1f02 drives Hard disk unit E ernal dr ives Contains wo Opt Opt...

Page 9: ...40 400 2 640 200 4 320 200 8 COlor 8 calors lean be speeified for each dotl Gradation 8 gradations available wilh the AvailClble on CI monochrome dedlcated monilor monilor 101 1 wlth a 640 x I 400 matrix Scr en char ac ter Display cClpacity 40 or 80 charaete s on each row Controlled by software conl gurat on The number of rows per screen is programmable Character eell 8 x 8 8 16 I Sereen conlrol S...

Page 10: ...ansion AAM PWB Hard disk dri I F PWB 5FJ I F PWB For MZ6631 MZ6 41 MZ6645 nandard MZ 1EII Additional Mouse Opt Attached to kayboard_ Available with the MZ 1 10 device MFO MFO unh Hard disk unit Opt Opt Opt Single drive increment Contains two drives Additional drive to be inualled in the System Unit External drives 10 1H Bytes Available with the MZ l F 15 For MI5631 only Avalillble with the MZ l F ...

Page 11: ...0cps impact pr nle r Color monitor MZ l 014 High resolutlon color video monitor for the Type t11 5500 MZ 5600 Serles CRT Display cepacity Video Input signal Sync Input Specificatlons Supply vol tage Power consumptlon Outer dimensio s Weight House HZ lxIO c rlo H1 IE21 12 Inches 90 deg deflection 640 dotl horllontally by 400 rasters vertically Independent RGB Input of TTL level wlth positive polarl...

Page 12: ...orizontal phase brlghtness System configuratlon Personal computer MZ 5600 series Color display 1 MZ 1D18 Cable altached 10 the unit lift standl Appearance color Office gray I I Accessories In erfacing cable Instructlon manual J Product out Hne Sped flcat ion The 8 floppy disk drive outline Product Cor use with the HZ lSOO series HZ SSOO ries and MZ S600 ser i es It has 0 be Interfaced via he exclu...

Page 13: ...nally in the HZ SSll Spec ldentical to the internal fica mini floppy disk drive unH tion of the HZ S500 1 7 Optional devices specifications for MZ 5600 Arithmetic and logical processor MZ M09 HZ IFIS internal expansion MYD drive Table 8 Designed to increase arithmet ic and logical operation speeqs 8087 2 Addit ional mini floppy disk drive MFD MZ F16 Table 9 Descrlption Additional mini floppy disk ...

Page 14: ...onnatted Sec tors capacity 512B format ed Sec ors per track 17 Disk used 2 disks Heads 4 Cylinders 317 Revolu ions 3600RPH Data transfer speed SOOKB s max between CPU aDd controller Recording dens1ty 9260BPI Recording meehod MFH Supply voltage 200V 60Hz Power consump tion 65 J Physical d1men sions 11 8cm wide 33 1cm deep 18 9cm high Color Office gray Produce ou line Speci fica cion i Hard di sk un...

Page 15: ...ut it has the funetion to synchronize the READY signal generated in the ready control circuit with the clock to send it to the CPU Tlle 8288 is the bus controller driver when the 8086 is operated in the maximum mode Command and control signals are decoded from the status output SO S2 from the CPU to issue control signal to the 1 0 device and the memory As a ccprocessor for a high speed numerical o...

Page 16: ...peed comparison Basic frequency SMHz us Item Ml lltiply single precision Multiply double precision Add Divide single precision ComEare Square root tan ex 8087 19 27 17 39 9 36 90 100 8086 emulation 1600 2100 1600 3200 1300 19600 13 000 17100 ...

Page 17: ...CONTROL cr u 8086 I LOCA LA DRI IS I I I PIC h B259A NA STER 1 1 PIC I I NOP I I I I 8087 I I L 1 1 I t 8259A STATl IS SLAVE r J r A lll LATCII r BUS CRTL IIIZ IIII08 1 1_ _ _ _ h c r eHT SYSTEM nATA BUS 16 f ox200 6 OX40 CULOI BIll If X 8 LATCHf r r p PI i220 I 1 v s KX Jl v 11 I SVSTE ADD BUS 3l SYSTEM UATA BUS 16 SYSTEM CONM n AUS AD5TB CTC LH 0082A I Cl I ATA RUS S l I I J I O C OIoIMANI AUS j...

Page 18: ... 8 l L J C t ru i ll O c rL CI I I L I f S U5 I t 09 L _____ 1 S rlt Da IA BUS t 16 1 l I Du il sOo U90 I a I 96 8 I I_ _ _ _ _ _ _ __ _ _ _ _ J 1 I 9 lo 10 I A 8 C SI f 0 A eus 1161 f C 5 0 0 8U5 16 o 1 1 O JI O 51 OUO Z 56 5 1 0 0 1 0 1 1 564 u T o I 1 HO 1 HO 1 I I I 10 If ftl S6J I 4 l 16 L _________________ ZOIltI ff 1 S6 E F l Z 6 I UO 5 Sla 1 I I 51015 1 UO I _ _ _ 4 10 3 2 J Htt SfN TH 0 I...

Page 19: ... RESET J Für reset of the 8086 CPU tI e alarm signal from the power supply unit and a rising edge at the time of power on are detected by the CR network RESET signal to tile CPU is internally synchronized with CLK by the 8284A For the alarm timing refer to the paragraph which discussed the power supply READY For the MZ 550lVS600 is normally a non ready system the ready signal is returned to the CP...

Page 20: ... 1t INr 1Nt AIIY Ilu fll 1I r 1ll K 1 0 CTC nrm rt Fig 5 RESET and READY circuit block diagram Table 1 4 Watt count of device 8MHz mode 5MHz mode System RAM 1PL ROM 1 0 other than below 1 0 510 RTC pSG PB 3 3 CTC 1NTACK 1NT RET 15 15 VRAM 1 0 380H 3FFH Memory other than above XACK or 1 XACK I 7 ...

Page 21: ...XACK XACK at the timing of 0 wait TI lI TI Tl 11 lW 14 T 11 1 I lLI AIII AL l rr _AUl Y I o 8MHz XACK XACK at the timing of 1 wait or morl o 6MHz OWAIT 1 I Tl 11 14 TI 11 CL A E _A o 5MHz XACK TI Tl TII 14 o 8 MII z 5 MJI Z aWA I T ALl _AlOY o Timeout ready o 8 mz 5MHz 15 waits omitted from figure Fig 1 6 READY signal timings ...

Page 22: ...Z IR16 Expansion DRAM and the MZ IRII Expansion RAM Board are available In regard to the VRAM 96KB is standard for the MZ 5500 5600 series whjch can be expanded 96KB more by the use of the MZ IR09 option 16KB of tlie ROM is used for IPL Initial Program Loader which js used to initialize the system and load CP M loader Since the CRT display 1s performed by the bit map method with the MZ 5500 5600 i...

Page 23: ... 132K B VRAM2 plane 1 32KB VRAM4 fllnne O 32KB VRAM1 plane 0 32KB RESERVED 12BKBI AlIxiliaryarea lor options Expans ion R AM area 256K BI Standard RAM area 256KBI XACJ I ROOOII 192KB Oivided nto the 8086 display cycle 000011 Read and write altempt from 8086 includes 1 to 7 waits C800011 COOOOII AOOOOIf _I 128KB XACK 8000011 1 40000 1 512KB 16bit BUS 2000011 XACK External Ready signal 0000011 Fiq 1...

Page 24: ...l ly the same as the MZ 5500 but 1 wait is inserted for the area 0 IFFH only in the 8MHz mode See Table 2 2 for the 1 0 bit map ii 1 0 user area For both theMZ 5500 and MZ 5600 three areas of 180 lAFH 0 wait 5MHz 1 wait 8MHz 300 33FH 3 waits and 3CO 3FFH are open for user s use In the 8MHz mode of the MZ 5600 1 wait i8 nutomatically inserted when XACK is returned in the 0 wait timing If XACK is no...

Page 25: ...Al AO OMAC 8237 100 7 X X Al AO PIO 8255A 100 7 X X X AO FOC pP0765 100 7 X X Al 0 PICt 8259A MASTER AOO 7 o X X Al 0 PIC2 8259A SLAVE X X x o X AOO 7 OMAC high order address laIch 104 7 o 1 X X X X X X X X PORT A 100 7 PORT C o X X Al AO Reserved 1 A2 Al AO Reserved o X X Al 0 1 X X Al 0 o A3 A2 Al 0 1 X X X 0 o X A2 All 1 X A2 All o X X X 1 1 o 1 o 1 X A2 Al 0 X A2 Al 0 X X X X GOC pP07220 WOC T...

Page 26: ...UT Centronia I F STROBE output LI IN Centronia I F ACK input OUT Not used AFTER P O Input mode FF H Mode input Input mode FFH INITIAL OEFAULT Output mode FFH Mode input 1 0 0 0 0 1 X X 1 Group A is used in Mode 1 2 Group B is used in M ode O 3 The desired bit otfthe output to Group C may be set or reset using the control register 013HI 4 The bit PC6 is an interrupt enable tlag INTEl and is set or ...

Page 27: ...00 WRCT Oedicated cassette Write signal No use LS175 101 MOTOR Oedicated cassel1e Motor signal No use OUT Indefinite 102 103 FOCRST F OC Reset signal reset when one POf H B nOH 100 RDCT Oedicated cassette Read signal No use LS125 101 SEr JSE Oedici ted cassette Sense signal No use Input IN 0 SW OFF 1 SW ON and C PU mode 102 DIP SW7 SW7 System DIP Switches See page l 103 DIP SW8 SW8 TL ble 2 3b MZ ...

Page 28: ...ry Description setup Description setup S o11 OFF High resolution OFF SW5 OFF 8MHz CPU clock OFF display 400 rasters used ON Medium resolution ON SMHz CPU clock display 200 rasters used SW2 OFF Normally OFF SW6 OFF 8087 numerical processor not used ON Seifeheck mode ON 8087 numerical processor used SW3 Fixed to ON ON SW7 SW4 Fixed to OFF OFF SW8 System switches of the MZ 5500 5600 are assigned to f...

Page 29: ...e of the CPU is asynchronous an interrupt request can be accepted at any time unless it has been prohibited by the software When the CPU receives the interrupt INTA i8 returned via the 8288 Bus Controller To which the 8259A forces the data bus high impedance As the second INTA is sent from the CPU via the 8288 an 8 bit vector is sent on the data bus y U IHT1I I Jr Tm lI nrT II iI IR 1J filC rz 11 ...

Page 30: ...s forced to return unless the ready signal was not returned within the predetermined tjme and NMl is issued to the epu at the same time to inform a timeout error 3 2 Handling of user interrupt i Hardware As there are several interrupt signals used for the MZ 5500 5600 expansion slots only the IR 26 is open for user s use The user must pay attentior to the following conditions when designing the in...

Page 31: ...ing modes are assigned to the 8259A PICo Level trigger mode 8086 mode Normal EOI mode Free nested mode lnterrupt routine programming mode 1 Jnterrupt address designation The top address of the interrupt processing 0 IOOn routine must be assigned at the start of the main routine As shown in the figure right the top address of each interrupt routine can be set in sequence from segment 0 offset 100H ...

Page 32: ...of the interrupt routine there is a need of informjng the end of the interrupt processing to the PICo MOV AL 20H OUT 40H AL OUT 30H AL IRET Example CSEG ORG lOOH XOR BX EX 1Programming the MOV BS BX interrupt address MOV BX lOOH 4 14 MOV AX OFFSET INT26 MOV BX AX INC BX INC BX MOV BX CS PUSH CS JAssign the 8080 model POP DS I CLI IN AL 42H JClear the mask register AND AL OBFH OUT 42H AL STI 1Inter...

Page 33: ...eognizes the interrupt Th e r e for e there i s a ne ed of using the deviee that ean elear the interrupt r equ e st by the s o ftwa re or the software that elears it on the 1 0 port As As tll e IR 25 int e rr oga t e s multiple interrupt by a software polling it i s so dcs i gned as to de t cc t t e device with the interrupt request on the r o port a en the interrupt elear and port output function...

Page 34: ...owing müdes are assjgned to the 8259A PICo Für more details refer to the 8259A specifieation sheet Level trigger mode 0 100H r 08086 mode Offset IR O Normal EOI Segment Free nested mode JIR I 0 100H 4 13 Interrupt routine programming mode 1 Interrupt addre s designation The top address of the interrupt processing routine must be assigned at the start of the main routine As shown in the fjgure righ...

Page 35: ...gister is cleared PIe mask register 1 0 address Master PIC 32H Slave PIC 42R The IR 25 should be progranuned as foliows IN AL 42H AND AL ODFR OUT 42H AL 3 EOI generation At the termination of the interrupt routine there is a need of informing the end of the interrupt processing to the PICo HOV AL 20R OUT 40H AL OUT 30H AL IRET 32 ...

Page 36: ...AX CS MOV BX AX PUSH CS J8080 model POp DS IN Al 42H Clear the mask register AND AL ODFH OUT 42H AL STI 1 I Interrupt enabled INTADR DB 0 0 0 0 INT25 PUSH AX Interrogate interrupt 1 1 PUSH DX MOV DX lCOH IN AX DX AND AX 1 i JNZ INTA POP DX POP AX JMPF CS INTADR J To next level interrupt routlne INTA OUT DX AX J Interrupt acknowledge Interrupt processing MOV AL 20H EOI genera ted and return l OUT 4...

Page 37: ...upt acknowledge cycle and thc illterrupt return cycle correspond to RETI of the Z 80 CPU A different CTC timing control lASTS circuit is provided for the MZ 5500 D nd the MZ 5600 and it has 3 waits for the 1 0 accessing timing of the MZ 5500 and 15 waits for the HZ 5600 CHo l IORQ 11Wtr CiC lt TOt RSmC I eIoe nArr on1rc vr nnT ClK TR L t Tmftf m 4l1 T CH4 7 llroincl t ____ _ 1f tI41rn Fig 4 1 Bloc...

Page 38: ...lowing deseribes the operational flow Interrupt proce66 I OV DX 240H IN Al DX Dummy interrupt acknowledge eyele f Interrupt cl nnel diS t i ct ion I OV OV OUT MOV OUT DX 260H Al OEOH DX AL Al 4 DH DX AL Dummy interrupt return cycle I Jnterrupt process I OV Al 20H EOI command OUT 30H AL I STJ j I I RET 1ii Cheeking interrupt ehannel MZ 5600 only The Z 80A CTC end out the interrupt vector in the int...

Page 39: ...pendent on the ehannel Ch 3 16 Ch 4 1 Ch 5 16 Ch 6 16 eh 7 64 Sinee the ehannel 3 is already used by the system ehannels 4 to 7 must be used Ex To generate interrupt at every lOms on the ehannel 6 Time eonstant CT 10 x 10 3 x 19200 16 12 MOV DX 216H MOV AL OC5H OUT DX AL MOV AL 12 OUT DX AL To disable interrupt to the ehannel 6 MOV DX 216H MOV AL 4lH OUT DX AL NOTE Range of the time aetor set in t...

Page 40: ...s possible to insert the board in any slot with exception for the HD interface board which shou1d be inserted in the slot l or slot 3 In this event th guide tab between the slot l and slot 3 must be removed Slot signal 1ine interface 1 0 signal lines of the board to be inserted in the slot must be treated as foliows LSTTL x 1 0 lS245 equivalent I o OUT UT c I STTL or standard TTl 6e the open colle...

Page 41: ...shed at a high to low transition of the signal During DH the s e two signals are issued at the same timing r o r ead signal 1 0 write signal Ihe IOWC signal is shorter by one CPU clock than the AIOWC signal and the write data is es tab lishe d at a high to low tl ansition of the s ignalt During DMA these two signals are issued at the s ame timing lnterrupt acknowledge signal from the CPU Ihe signa...

Page 42: ...rrow high per od clock of 1 3 duty CLK4M is 4MH and OSC is 14 7456MHz clock RESET Out Power on reset signal which is normally low RSTSW Out The signal is forced low while the front panel RESET switch is kept depressed At the moment the switcll is pushed an NMI is issued to the CPU See the next page for the timing chart 5 3 1 0 address setup When an 1 0 port is to be expanded on the expansion slot ...

Page 43: ... IBOn CLK 6 IOACC AO vAI5 BHE 0 P C DO V DIS 2 1 0 read 8MHz 3 wails 1 0 address 300H 33FH T CLK 6 IoA c e I 1 0 Ab BHE TI C rORe I DO DIS 3 1 0 read 8MHz XACK 1 0 address 3COH 3FFH l LI b 10 CC AO ÄI l BHE fORe Do DIS 4 _____ Tw Iw Iw T w __ ____________ ___J ...

Page 44: ...IoACC 1 C A fl A S B E D lowC Arowc 1 DIS 5 1 0 write 8 z 3 waits 1 0 address 300H 33FH LLK b 1I T2 T IoACC I Aft IS BHE D C IOWC AroWC D O DIS 6 1 0 write 8MHz XACK 1 0 address 3COH 3FFH Ti T2 C LK G L l IoAcc I A1ir AJr J BHE TI ___________________L IOWC AIOWC DO rv DI5 XACK ...

Page 45: ... PS 2 16 bit output port 1 0 address 320H When only ward write is done Word output MOV DX l80H MOV M OUT DX AX Insignificant date f 5 S D8 will be stored in the other byte when the byte write is done 4 ALt 1 D7 ÖW td S C D A A9 A7 Ah Ll 3 len the high order and low order bytes are written independently Word output M V DX 180H 6 AA M V OUT D AX Low order byte output MOV DX 180H MOV AL OUT DX AL Hig...

Page 46: ... OMA transfer and uron compl etion r e leases HOLD In this manner the 8237A deprives the CPU of the bus for six clocks If the epu goes into th p bus cycle after rp c e i vin g HOLD w its are inserted for six c10cks at the maximum and accessing is continued thereafter as if nothing happenp d As four channel are provided for the 8237A channel 1 for the MFD channel 2 for the RAM refresh and channels ...

Page 47: ...A16 19 DO 15 16 8 Cvmmand CLK RIlY HRQ DREQO DREQO HL DACRO DACKO Ta 1 0 siot DREQS DREQ3 AO DREQ3 I DACK3 A7 ADSTB DREQI DREQ DBO DACKI DACK DB7 DACK2 f f IOR CTC I JOW DACK2 MEMR READY MEMW C K DACK2 DRAM refre5h cir ld 40 Q 1 J Fig 6 1 D circuit block diagram ...

Page 48: ...As the HOLD conversion circuit receives this sjgnal it makes the CPU in the non ready state and the system bus is released At the same time the hold acknowledge signal HLDA and the DMA enable signal DMAE are returned to the DMAC to perform the DMA transfer The 8237 DMAC controls DMA transfer of any 16 bit area 64KB represented by address signals AO A7 and A8 AlS which latcl DBO OB7 with ADSTB at t...

Page 49: ...A Reserved r o AEH to OlH B Reserved r o AEH to 02H C SFD interface MFD interface r o AEl1 to 04H D Reserved r o AEH to 08H E Reserved 1 0 AEH to lOH F Reserved 1 0 AEH to 20H G Reserved r o AEH to 40H H User 1 0 AEH to 80H 1 Hardware 1 Channel 3H is used or the D channel 2 Only byte transfer mode is applicable for the DMA transfer 3 DREQ3 channel 3 DH J request must be outputted by the open colle...

Page 50: ...ler 2 Assign on1y the channe1 3 for the DMAC Never reset and mask the chaI nel 2 wi th the master clear command for examp le 3 Bef re the DMA send BOR to the 1 0 address AEH to open the user DMA 4 64KB is the maximum that can be subjected to DMA at one time 5 Assign the single transfer mode for the DMA operation tl 4 7 ...

Page 51: ...ter and data of 32KB are transferred to the main memory area to 47FFFH at every 100 microseconds A D convert er 8 ftß8 IAl 1 _ tth1 DO v ADB AD7 D7 t 5V 6 1 AOO 1 1 1 Do I DO DIS rORl 4McLK D7 Di Arowc Aq A A7 AG A5 A4 1 3 IR 2G A2 1 8 Counter Qt I r D DAck 3 a r c RESbl 5V R5TSW D g CLR Fig 1 Circuit example ...

Page 52: ...t DHA start address to 40000H I MOV AL 0 OUT 06H AL OUT 06H AL Se t DMA add ress offset MOV AL OFFH OUT 07H AL MOV AL 7FH Set DMA word set DMA transfel i OUT 07B AL size to 32KB J MOV AL 47H OUT OBH AL CH3 MOV AL 03H OUT OAH AL Clear DMAC eH mask MOV AL 80H OUT OAEB AL Li IN AL 40H AND AL 40B JZ i Li MOV AL 0 OUT OAEB 0 XOR CX CX XOR DX DX INT 224 END Enable 1 IR 26 is used simply as an input port...

Page 53: ... sn Dl H TIO J f WMU HRQ psc WDATA DRO wrc r 1 HLDA R D YFO V Lt SYNC I _ __ j1 MOUT IN Oß 0 W ttdew D130 1 t1 H DßI 1 Pß7 WeLt SltK i _ REAP DATA M010R oN Dltü bus I J 7f L 0 P60 1 lO PB1 LOt l 100 psCr A Y J q 12 Fig 7 1 Mini floppy disk interface block diagram The recorcling surface of the mini floppy disk is divided into fo rt y tracks along the radius Fig 7 2 Track number begins from 0 and en...

Page 54: ...ferred between the memory and FDD via FDC under th e blls control by the DMAC The receive circuit from the MFD drive to the FUe is simplified by the use of the SED 9420 VFO Data Separator le As it internally incorporates the window clock 2 by which the read data signal is fetched from the floppy disk drive which is then divided into the clock pulse and data pulse and the timer circtiit This contro...

Page 55: ...e 640KB 200 disk on the MZ 5600 it is possible to read from lllci write to the disko However when using the 320 B disk only reading is possible as it is designed to read the disk which has been created by other mod e l of personal computers such as the MZ 5500 To read the 320Kß disk 0 1ll1lSt be specifi ed or the FD l gical number For more details refer t C th e CP l 1 86 and MS DOS manuals 256 B ...

Page 56: ...ram The the following disko are requfred in order that the FDC r eads fr om or writ e s to 1 I 2 3 4 The DMA request signal DRQ is issued from the FDC to the DMAC and VFO data separator 1 As the DMAC receives DRQ HRQ request is sent from the DMAC to the CPU As the CPU receives HRQ the bus line is opened and HLDA is returned To which the DMACreturns DACK to the FDC Datfl are transferred between the...

Page 57: ...ors 16 sectors track Tracks 80 tracks side Recording surface Two sides Track density TPI 96 Recording density BPI 5922 Data transfer rate 250KB s Recording method MFM Transfer methou MFM Access time Average 94ms Track to track 3ms Settling 15ms Revolutions RPM 300 4 ...

Page 58: ...ector numbers I to 17 are assigned to represents the specific location with the track number sector number and head number 0 to 3 Fig 8 1 also shows the soft sector In the 10 field is contained the secto r address information track head sector which is normally used to acc e ss the specified sector For better reliability retrial i6 made possible If recovery was not J CII DiSK 7 1 successful with r...

Page 59: ... Tl l rr D MBIS550 MZ I F M815546 PHE CCM 1tN GENlRA10R MHA Gr J RAr 00 tIX LSI ...

Page 60: ... the firmware of the interface This firmware automaticnlly starts to test ready read write seek the hard disk upon power on If any error has been encountered during the test the condition is displnyed on the video unit by the OS Table 8 2 640KB FDD specification physical CP H 86 spec Recording capacity 10 7MB t 10 7MB Disks 2 Heads 4 ecording surfaces 4 Cylinders 317 Tra cks 317 x 4 tracks 673 x 2...

Page 61: ...d the ACK signal from the printer applies the interrupt CPU side ID Hn 1R fRT 4 1 825SA mode to the CPU 82ssA e5 RD RESfT Atj AI pes PAS pA PC6 PBS FC3 PB PB2 IOCS Printer side STRöBE DATA IV DATA8 ACK BUS I1 PE SElECT SRES 11 V 11 mark lKohms pulhip resistor control procedure hiODEl outr t I PAO I PA1 PC1 PC6 PCS PC PCS ALK OUT om INT hiODEO outpvt PC2 pet üm f PCO hiODEO PBO li1 ut I IN PB1 Cent...

Page 62: ...the printer 3 DATA2 4 DATA3 5 DATA4 6 DATA5 7 DATA6 8 DATA7 9 DATA8 10 ACK In Completion of data or function input 11 BUSY Out Data receive enable low 12 PE Out Paper empty high 24 SRES In Reset signal 25 SELCT Out Indicates the select receive enabled conJition high r I 14 23 GND 18 Error insertion protected Timings BUSY I m Ur 1 n 1J IR FRT n f ATA TRöBE ...

Page 63: ... IB 6 NOTE The machine language routine 15 required for the MZ 2000 series 9 3 Making a hard copy of the video screen Since the MZ 5500 5600 has the multiwindow capability it can be copied on the printer with windows overlaid in the display screen CP M 86 and MS DOS incorporated hard copy function Push the BREAK key first Push the COPY key in the wait state in which tiOle the CAPS key is blinking ...

Page 64: ...10 1 Specification Input output method RS232C bit serial input output Channels 2 channels Channel A BSC conforming Chanriel B Code used JIS 7 channel code system J1S 8 channel code system Baud rate 110 150 200 300 600 1200 2400 4800 9600 BPS Transmission rnethod Half duplex Channel A and B Transmission control procedure Non procedure Data format l stop bit Parity option of even odd and non parity ...

Page 65: ... is permitted Data transmission is enabled when ON Data trnnsmission is disabled when OFF NOTE Even when the signal 1S turned OFF from ON a maximum of 2 bytes of data may be sended until transmission is eompleted 6 Receive enable READY DTR Out The signal whieh indicates whether data input is enabled ON Enabled OFF Disabled 7 Signal ground SG 8 Data set ready DR DCD In The signal whieh indieates wh...

Page 66: ...eceived by the device The signal which indicates reception of the caII signal from the line l4 Receive signal element timing RT In Input signal element timing signal in the synchronous transmission mode IS Transmit signal element timing ST2 In Output signal element timing signal in the synchronous transmission mode NOTE Not supported by the standard software BASIC CP M 86 MS DOS I G3 ...

Page 67: ...h l masked in the es monitoring mode See the CP M or MS DOS Manual 10 3 Process outline Transmission BASIC mode Cp tl mode MS DOS mode RS ON 1 1 Device in error 1 2 I Transmit byte of cp t1 115 D0 5 mode RSloff RSlOff no RET te ep M RET 10 BASTC RE 1 10 M POj I I I one data ...

Page 68: ...S tn BASIC ho lAll shal1 be the receive data RET TO C F M RET 1 0 BASIC Error Rn 1 0 RET 0 15 DOS NOTES 1 Data will be received in the divided mode But the data input when READY is OFF will be inval f d 2 Although READY goes OFF upon occurrence of 1 receive error in the CP H mode depression of the CIRL Cl key clears the error 65 ...

Page 69: ...SD RD 3 DC 3 RD es 5 5 es READY 6 DC 6 READY DR 8 8 DR ER 12 12 ER SC 1 7 9 1 7 9 SG Others are open 2 MZ 5500 5600 to from MZ 3500 A B A B Signal name Pin No Pin No Signal name SO 2 1 SD RD 3 3 RD es 5 5 es READY 6 4 READY DR 8 7 DR ER 12 6 ER L SC 1 7 9 8 PO 9 10 SG Others are open Dip switch 5 ON 6 ON 7 OFF ...

Page 70: ... 11 22 CI RT 14 14 RT ST2 15 15 ST2 SG 1 7 1 7 SG Others are open Use the MZ IC36 cable 4 MS 5500 5600 to from the modem CClTT V24 compliance A B A B I Signal name Pin No Pin No Signal name I SO 2 2 SD RD 3 3 RD RS 4 4 RS CS 5 5 CS READY 6 OR 8 6 OR CD 10 8 CD CI 11 22 CI ER 12 20 ER STI 13 24 STl RT 14 17 RT ST2 15 15 ST2 SG _lL_ 7_ 1 7 FG SG Use the MZ lC40 cable r7 ...

Page 71: ...uxiliary IN F4 Auxiliary OUT F5 List Out Input device Output device Key Port A Port B Screen Port A Port B Printer ON ON ON ON ON F9 Exit FI0 Assign and exit Now transfer the file using the PIP command eTransmit side A PIP AXO A ABC LST J eReceive side A PIP A ABC LST AXI NOTE With this PIP command only the file composed of the ASCII code such as the list file can be transferred To transfer the bi...

Page 72: ... the case of the example72 Althotigh it is identical to the CO M 86 and BASIC programming example for the example l reference must be made to the MZ 3500 manual as it differs in the RS232C parameter setup 09 ...

Page 73: ...the second byte assigned to the entry code Description of special keys Al SHIFT key Used 10 place the keyboard in the shift mode used with other keys Operation of the SH I FT key alone is invalid no code is transferred to the CPU B CAPS key Used for shift character selection Operative only in the normal mode If used with the SHIFT key shift and normal selection will be reversed If the CAPS key alo...

Page 74: ...parity error occurred UC is 1 The CPU sets STC to one to complete the transfer seQuence Keyboard When STC is set to zero the keyboard reads the result of the parity check When STC is set to one it sets OK to one to enable an interrupt from the CPU and completes the data transfer sequence 1f a parity error was detected the keyboard terminates the data transfer sequence then tries the same data send...

Page 75: ... data is regarded as correct While the search cycle is 5 5ms it is ex tended to 16 5ms if a bounce occurs t YI Y2 fwutH IlAlAI _ _ __ ___ _ _ lJl l I A JA _ _ __ _ _fLJl f L_ 1 c K Y2 IJATA Fig 11 Key search sequence for two key operation is th same as that for single key operation When two keys are simul taneously pressed key data for the first and second keys are successively transferred 11 4 Ei...

Page 76: ... CPU interrupt strobe input ISTC GND B RD N C 9 PSEN N C 10 WR N C 11 ALE N C 12 19 DBO DB7 IN Returns signals from the keyboard 20 Vss IN GND 21 P20 OUT Send data to the System Unit lOK 22 P21 OUT Data enable start signal SRK to CPU 23 P22 OUT Enables data send to the mouse ICTS 24 P23 N C 25 PROG N C 26 VDD IN 5V 27 30 Pl0 P13 OUT Strobe to the keyboard 31 P14 OUT CAPS indi ator drive signal 32 ...

Page 77: ...oder outputs are counted in the counter U1 The value counted in U1 is read by the U2 4 bit microcomputer in the given cycle to be accumulated in the X axis pulse generator U2 internal counter The U1 is reset as soon as the value has been read and performs relative counting Fig 12 1 X Y encoder of the mouse Rt all times As the U2 reads the data request signal CTRL in thegiven cycle from the keyboar...

Page 78: ...ndition immediately before the data output st rt bit is issued X Y data X and coordinates within TA and TB are issued as dat a A and data B Relative coordinates are always issu ed TCL min 500pS Control L pulse width TCH min 50 lS Control H pulse width TD max 750 S Output data reply time Encoder input wave form X ENC Y ENC Phase A Positive rotation Phase B H 11 L Direction in which phas e B becomes...

Page 79: ...ENC A c e l O W 4 1 YA c4 2 GND 8 GND Vtid L 4_ _ 1Ri KIO CC 12 Yd d E eto o l6 Jl 15 CI 8 2 1 N i r 13 ce J3 C I r SHl in He KO 0 10 r tu o n ce 11 0 1 2 c 12 Ha N 13 K4 14 K5 Ra v I K7 Rl S EX X V 15 J J ca I I I S5 I Ba I I _______ J C2 OD I lF VCC CI 10 lOV 4 j loopr IOOff Fig 12 2 Mouse circuit ...

Page 80: ...al time clock and it has the features shown in the table Although the RP5C01 is accesseQ with the 1 0 address 220H to 22FH the s e tu r time of lORD and lOWR is delayed via the LS74 D flipflop to create RD and WR signals because the read write setup timing 1s rather slow Table 13 1 Features of the RPSC01 4 bit bidirectional bus DO D3 4 bit address input AO A3 Internal timer to keep time hours minu...

Page 81: ...ut intervention of the CPU With ADJ H the seconds are reset to zero when it is within 0 to 29 seconds lf it is within 30 to 59 seconds the seconds are then incremented AO A3 4 5 6 7 Address pin to be connected with the address bus of the CPU 1m 8 1 0 control input Low for input from the RP5C01 to the CPU GND 9 OV WR 10 1 0 control input Low for input from the CPU to the RP5COl DO D3 11 12 13 14 Bi...

Page 82: ...detects a power down and then sets the circuit to the power down condition When power is on to the personal computer Tri and Tt2 in Fig 2 l3 1 are active so that SV is supplied to the RPSCOi and the backup battery is being recharged When power is off it makes Tri gone inactive f rst then Tr2 This isolates the circuit on the right of Tr2 Then the backup battery supplies power to the RP5COI whi c h ...

Page 83: ...ay register 9 y l month counter A lO month counter x x x 12 hour 24 hour selector B l year counter Leap year counter C 10 year counter D Mode Timer Alarm M ode register regi s ter EN EN Ml MO E Test Test Test Test Test regi s t e r 3 2 1 0 F Re s et 1Hz 16Hz Timer Alarm controller etc ON ON reset reset Mode 01 10 11 D3 D2 Dl DO Conte nts Contents x x x x x x x x Block 10 Block 10 x x x 4 bits 4 bi...

Page 84: ...ted up at the same time the year is counted 12 2ll hours selector The 24 hours system is adopted when DO l The I t hours system is adopted when DO O With Dl l PM is selected With D1 0 AM is selected Reset controller 16Hz lHzCK register CA3 A2 Al AO l l l l F All alarm registers are reset with DO l Minutes above seconds are reset with D1 1 16HzCK pulse is ON with D2 0 1HzCK pulse is ON with D3 0 Ad...

Page 85: ...te To write the 4 bit da ta 5H in the STAAT addre s OA of Mode 11 Select RAH block Set mode register 0 0 0 0 0 X X 1 0 OA X x 1 1 SSUB Write data in RAM NO ESUB f N o 2 Read To read STAAT of Mode Select RAM block Set mode register D D D Do X X I O OA X X I I Read RAM data E N Nibble NO CALL SSUB MOV DX 22AH MOV AL 05H OUT DX AL CALL ESUß HOV IN OR OUT RET HOV IN AND OUT RET DX 22DH AL DX AL 03H DX...

Page 86: ...se registers to generate sound and manage it and the CPU is therefore open for other jobs Not only the PSG ineorporates the sound generating funetion but it also has the 8 bit parallel 1 0 port on which the mini f loppy di sk in ter f nee drive select sfgnal SLO SL3 motor on signal and address bank selec t signal AOOOOH BFFFFH are sent Three sound signal outputs A B C from the PSG are ORed in the ...

Page 87: ...ut 5V supply Analog output channel B Analog output channe1 A OV 1 0 port 15 16 17 8 19 20 CLOCK RESET A8 BDIR BC2 BCI In In In In In In Tone noise envelope generator timing reference input 2MHz Input of a 10w 0 signal to this line at the start it resets all registers Auxi1iary address bit which is provided to permit a memory space expansion in addition to the area specified by DA7 DAO Bus directio...

Page 88: ... current address are sent on the PSG CPU bus 1 0 0 LATCH ADDRESS 1 0 1 INACTIVE 1 1 0 WRITE Ta PSG Indicates that the bus retains the data in the register latched at the current address 1 1 1 LATCH ADDRESS 21 28 DA7 DAO In Out In the data mode corresponds to the register array bits B7 BO in the data mode In the address mode DA3 DAO are used to select the register number and DA7 DA4 to comp s the a...

Page 89: ...xpanded to 192KB when the option is used The hardware character generator is not provided as standard 01 ncorporates the pallet function and color priority function Possible to handle eight colors and eight monochrome tone Table 15 1 Mode specification Color mode Color CRT Possible to make choice of eight colors for each dot for three planes of 0 I J and 2 Possible to assign eight tones for the ba...

Page 90: ... 02in5 I 0 82J19 r 56 49Hz VS U I I I L 16 09ms I U17m i o VIDEO I 63 695 JlS r l d ilpl V 200 I 15 699KH l i 4 47 HS W i 698 c I I d I I V I DEO 16688rre I I t O 19ms 59 92 Hz VS I 12739rns UI I 2 42ms I l VIDEO I a b 640x400 640x200 4 8Sps 1 _69E __ 320x400 5 0 us _ 42 us At the base of GDC 3 73 Ps 3 73 s 640x200 320x200 At the base of GDC c 9 S0 Js 9 78 Js 7 82 1s I d 5 03 ls 4 75ps 6 70ps I Cl...

Page 91: ...d three data for displaying from planes 0 1 and 2 Which data should be read is directed by VDS of the WDC However giving the address 30000H 3FFFFH GDC for the display address may cause the display to distort NOTE 2 When the CPU accesses the expansion VRAM area of C8000H CFFFFH D8000H DFFFFH E8000H EFFFFH NMI will not be applied to the CPU even if the expansion VRAH does not exist Normally NMI is a...

Page 92: ...achine language Gnc Short words for Graphie Display Controller vuPD7220 which is used for the MZ 5500 5600 VRAM Video RAM CPU GDC PLANE2 EXPANSION PLANE2 PLANEl EXPANSION _ PLANEl PLANEO EXPANSION PLANEO UNIT 16 bits Unit 8 bits E8000 14000 EOOOO 10000 00000 D8000 DOOOO 08000 C8000 04000 I J 16KW 32KB 00000 COOOO EXPANSION Expansion VRAM Fig l5 1 VRAM memory map d 5 ...

Page 93: ...3 3 VBP 34 38 38 130 H H 1 0 I 4 I 0 I 5 Others I NOTE 2 J NOTE l NOTE 2 IDI3 MZIDI3 IDI4 MZIDI4 IDIB MZID1B NOTE I Set to L R 1 2 lines by the CSRFORM conunand NOTE 2 Set to IM l by the SCROLL command Set to double value of 640 dots mode by the PITCH command Set to DGD 1 by the VECTW command For graphics and display refer to the APD7220 User s Manual CAUTION 320x200 mode is not applicable for the...

Page 94: ...have its priority specified and it allows overlay of windows 3 When there ar e three VRAM planes it is possible to display by plane or overlaid display of two or three planes 4 It is possible td make direct output of the inputted address without the use of the window funetion WDC registers 1 RNO register 1 0 address 110H Register number 0 12 is set IX x x x RNO RNO O 12 2 Priority register 1 0 add...

Page 95: ... windm J 1 4 P Bias address high 5 J VRAM data select 7 6 Bias address low For windöw 2 8 Bias address high 9 1 VRAH data select Bias address low For window 3 11 10 Bias address high 1 VRAM data select 12 Fig 1 5 3 Register setup The priori ty register and the window register must be set after writing each register number to RNO register Since the RNO register increments by one automatical1y each ...

Page 96: ...cept the following different priority values must be given NOTE 1 When only one window was set to mapping RAM l it does not matter even if the same value other than 0 is set for all NOTE 2 If windows are not overlaid as in the figure right it does not matter even if the same alue other than 0 is set for all NOTE 3 When all priority registers are set to 0 it disables the window function so that the...

Page 97: ...a A which begins with WDA is displayed in the area B which begins with VAD SAD is the display start addr ess to he set to GDC Fig lS 6 VDS VDS controls the VRAM plane output bit 2 1 0 VDS I I I 1 For the plane R or one plane For the plane G For the plane B As shown above VDS has three bits for ea ch window which are used to perform any plane display or overlaid display of two or three planes ...

Page 98: ...trols the location and area o f window in the display screen area Bit o 1 2 3 4 5 6 7 30000H 3000lH NOTE The mapping RAM cannot be WO W1 accessed from the epu 3007FH 30080H Not used 303FFH tttiJIt tJ W2 W3 WO W1 W2 W3 1 1 Column map Row map 1024 words 128 words Fig 1S 8 The mapping RAtl exists on the GDC memory map as shown in Fig lS 8 It has to corresponds to the display screen when the mapping R...

Page 99: ...t the time of 320x400 and 320x200 dots mode only even addresses are ef fective The left margin of the display screen is the address 0 and the one that follows is the address 2 o As one bit of the column map corresponds to dot of the display when djsplaying under the 200 ras ter mode for the MZID13 MZID14 and MZIDI 8 the wind ow may be specified in an increment of dot for the horizontal direction ...

Page 100: ...y should be set in succession at VSYNC Set P iOrity 1 As VSYNC is with IRQ of the master 8259A this interrupt may be used END Priority VHA and VDS may not be programmed one at a time necessarily they may be set altogether if possible However the mapping RM shCluld preferably be programmed for a window one at a time during the vertical flyback time in order to prevent distortion in the display Use ...

Page 101: ...olling within one window In such an occaslon the following screen setup and seraIl may be possible i Two windows scrolling in different directions ii One window scrolling and two windows not scrolling VRAM CRT 5A02 7 SAI l a b c cl e f 3 h j k I lY1 n J B c D 2 J q i j k L M N 0 P R r tJ V w X Y Z 1 2 I 2 J h 7 A A A B 8 B c C c D D D E E E F F q 4 q EFq H c cl B ß 8 2 1 J K L e f ce C MN 0 P g h ...

Page 102: ...ping RAM But any desired area m y Hot be specified as the v dndow set in this manner i8 on the corresponding loeation on the VRAM as it is addressed by the same VMA WDC initialization The WDC needs the following prior to sending of the START eomrnand 1 All clear of the rnapping RAH 2 Setup of the rnapping RAH priority VMA and VDS für the screen to be displayed first qq ...

Page 103: ...y I I I I I i j2 S 1 0 1 Y 6 C 4 oS b ö fl 1 Y Q 1 J 1 t9 j 1 f 0 I 0 0 J j Ro Mqp p 1 As shown above the mapping information must be written after dividing it into the horizontal eomponent and vertieal eomponent Only 16 points must be programmed f or setting four windows sinee one bit eorrespond to one window and only the revised portions are written The mapping RAM must be written us i n g the g...

Page 104: ... dot mode is 640 dots l lhen horizontal dot mode is 320 dots The resolution must be selected using the SYNC command of the GDC and thp address 130H Mode select register 1 0 address lZ0H DZ Dl DO I x I I I 0 Color mode 1 Monochrome mode 0 Don t care O Normal color display 1 Plane preference mode f NOTE DZ must be programmed 0 in the case Qf the monocprome mode As the block diagram uf th e VDC2 is s...

Page 105: ...0 0 1 0 0 1 1 o 1 1 Oll 1 011 1 0 1 1 0 1 1 1 0 0 0 0 0 110 0 1 10 0 1 0 0 11 0 0 l 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 O 1 0 0 1 0 110 0 110 0 1 1 1 0 1 1 0 1 1 0 1 1 011 1 110 0 Plane 1l t Plane 0 Plane 1 data Priori plane 1 and plane O ty order is given for The four data of plane kinds of data 2 would composed of not the plane 2 be obtained if o was set when there is a data in the pla...

Page 106: ...et number for window 0 background color 126H D2 D1 DO Pallet number for window 1 hackground color 128H D2 D1 DO Pallet number for window 2 background color l2AH d D2 D1 DO Pallet number for window 3 background color Border color register 1 0 address l2CH Specifies pallet number of border color Border color is th e co l or outside the window 12CH D2 D1 DO Pallet number for border color NOTE As a co...

Page 107: ...n the pallet register As data written in the video RAM are read to be displayed at the same time from planes 0 1 and 2 it may constitute a number 0 to 7 if they are assumed to be three digits binary number having the plan 0 for LSB and plane 2 for M SB which is used to be the pallet number What color be displayed by a pallet number depends on the color number set in the pallet register which is di...

Page 108: ...ght Dark NOTE Since correct display is not assured for the MZ1D13 MZ1D14 and MZ1D18 due to restriction by the CRT it has to be so programmed as to obtain color in the border portion Monochrome CRT tone display As s en ln the color number list above tone display is enabled with the monochrome CRT composite video input is connected Composite video input Video signal tone coexists with the sync verti...

Page 109: ...or I 12V Yellow 2 GND Black 3 GND Black 4 SV Yellow Pin No Signal name Wire color 1 12V Blue 2 12V Yellow 3 5V Red 4 SV Re 5 ALARM Orange 6 GND Black 7 GND Black 9 GND Black The signal ground SG shares the line with the frame ground FG Alarm signal Hoth types of the power supply units have the ALARM signal by which an abnormal condition in the DC output is detected as caused by a source supply fai...

Page 110: ...ded However the power supply unit may sometimes not reeover its normal funetion imrnediately after removal of the enuse in such event turn the power switch off wait for 30 to 40 seconds then turn power on lf power is not supplied on even after this there may be a possible opening of the fuse or a trouble As no overeurrent protection i8 done to VGG 12V eare must be exercised not to short the line l...

Page 111: ... is as shown in Fig 2 Almost all commands of the 8087 data tran fer arithmetic operation comparison are executed with the register ST 0 or between ST 0 and other register ST 0 7 or the memory The r e are s even kinds of data formats that ca n be handl ed Fig 3 but they are 79 S T 0 S T 1 S T 2 S T 3 S T 4 S T 5 S T 6 S T 7 o co nv e rt ed into the format when fetched Fig l 8087 registers insid e t...

Page 112: ...eell nurnber The exponential part is provided for easier data comparison and has been added with the above mentioned bias The following is an example to compare 5 00000101 BIAS OOO100 40 11011000 7FH 01010111 10 00001010 BIAS 10 OOI 21 00010101 7FH 10 1 100 7 11111001 BIAS Olll OOO 11 11110101 7FH 0111 100 If not biased it needs to distinguish comparisü between the same signs d different signs But...

Page 113: ...EX AX 9 MOV AX 2 10 MOV OS BP AX 11 MOV AX O 12 MO DS SI AX 13 14 WAIT 15 FINIT 6 WAlT 17 FILO BX 8 WATT 9 FIAOO OS BP 20 WAIT 21 FJST OS S11 22 WAIT 23 24 MOV OX DS fSI 25 AND OX OFH L6 ADD OX 30H 27 MOV CL 2 28 I T 224 29 30 XOR CX CX 31 XOF OX DX 32 INT 224 33 END This progrnm adds the contents in 20000B with the contents of 20002H and the result is stored 1n 20004H using the 8087 llO ...

Page 114: ...ummy cyclp the CPU memory th BIU creates the physical address from DS executes J and BX and dummy read cycle RQ pulse i8 issued tu the epu is execu ted to reques t f or the bus privilege Upon receiving of RQ GT Memory read cycle is executed pulse is sent out to from the address implied by the release the bus for use data pointer to rush the data if satisfactory in ST O The data in ST n i8 stored i...

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