Sharp MZ-350C Service Manual Download

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Summary of Contents for MZ-350C

Page 1: ...y Configuration 7 3 CPU and memory 12 4 CRT display 25 5 MFD Interface 52 6 R232C Interface 72 7 Printer Interface 7g 8 Other Interface 81 9 Power Circuit discription 37 10 Keyboard Controller Circuit discription QQ 11 Seif check functions 94 12 IPL flow chart 103 13 Circuit diagram P W B Parts list Guide SHARP CORPORATION ...

Page 2: ...ontroller Parallel I O port Serial I O port Counter Clock Model 3531 includes a single double side double density mini floppy disk and 128 KB Model 3541 hastwo double side double density mini floppy disks and 128 KB Z80A microprocessor x 2 8K Byte ROM 8K Byte ROM 64K Bit DRAM x 16 Chips or 8 Chips 16K Bit SRAM x 4 Chips 16K Bit SRAM x 1Chip 16K Bit SRAM x 1 chip 4K Bit SRAM x 2 Chips TH SP6102R001...

Page 3: ... Molded Size W x H Automatic repeat occurs 0 64 seconds after 2 Two key rollover contmuous depression of the same key POWER Alphanumeric keys Color xL Office gray 467 x 35 x 190 Weight About 1 5kg 3 3 Ib Keyboard layout Refer to the page 7 IN CIRCUIT DIAGRAM 1 3 MZ 1U02 Outline Specifications Expansion unit for the MZ 3500 series CPU which can beattached to the rear side of the main unit Optional ...

Page 4: ...KB 32KB basic 640 x 200 dots Two screens ______ 640 x 400 dots One screen ___ SDISP ODISP CHANCE DISP GCOLOR CLS PSET PRESET LINE GTABLE CIRCLE PAINT GINPUT GDISP GPRINT GREAD GENTER GCURSOR GSCROL SYMBOL SCALE 96KB maximum expansion 640 x 200 dots Six screens 640 x 200 dots Two screens 640 x 400 dots Three screens 640 x 400 dots One screen Screen designation for two video units Oesignation of Out...

Page 5: ...e expanded up to a maximum of 256 KB This Option plug into the expantionbox in slot 1 or 3 LSI Memory and user area Basic Expansion 64KDRAM x 8 64KB 64KDRAM x8 128KB Total capacity of the main CPU RAM BASIC RAM BASE SYSTEM AREA USER AREA Main CPU only 128 KB 57KB 80 KB Useof MZ 1R06 192KB 128 KB Using eight 64K RAM s on theMZ 1R06 256KB 208 KB 4 ...

Page 6: ...uorescent color P39 green long PERSISTANCE Total number of display characters 2 000 characters 80 characters x 25 lines Display capacity 640 horizontal dots 400 Vertical lines 220 x 145 Method Horizontal Separate input TTL level 20 86kHz Vertical 47 8 Hz 29W power consumption Molded Color Size W x H x L 3 Office gray 324x310x356 Weight 7 2kg Vertical synchronization contrast brightness CPU connect...

Page 7: ...MZ3500 1 8 System configuration of Model 3500 Keyboard M2 1K02 MZ 1K03 MZ 1K04 MZ 1K05 1 1 Printer I02824E l l Option MFDl l CE 331M l l Model 3541 Model 3531 MZ 1F03 6 ...

Page 8: ...only exist immediately after power on and the System executes IPL under this condition and that the system thus loaded will automatically assign memory area for SD1 SD2 and SD3 MAIN CPU SUB CPU MAS MA2 MAI MAO 17 p 171 r r r r cooo BFFF 8000 7 FFF J 4 0 0 0 3FFF 1 0 0 0 0 1 RAMA 4 RAMA 3 RAMA 2 1 1 ROMB 1 0 1 0 1 0 1 1 1 1 T FFFF T l RAM COM f nAn 1 i tiOO RAMA J 1 MSI 0 L MSO 0 L 2000 OFFF 0000 l...

Page 9: ...y allocation state to SD1 and Starts to load DOS from the System floppy disk Signal generated from the CR networkand power supply Output Signal from the main CPU port MAIN CPU START a Main CPU reset time b Main CPU IPL load time Memory Map Data 1 ROM B is tested to determine if ROM s are present 2 The ROM IPL functions under control of the mainCPU at first but later it functions under the sub CPU ...

Page 10: ...is addressedby the sub CPU 5 Address 0000 of the sub CPU is ROM address 0000 The memory area above ROM address 1000 cannot be used by the sub CPU because the main CPU initial program has been loaded there 2 2 SD1 SYSTEM LOADING CP M SD1 determines which operating system is in use The system is loaded in the CP M Control Program for Micro processors mode MZ3500 Main CPU logical address during IPL O...

Page 11: ...eterminesmemory allocation BUSRQ H OUTPUT l ISOLATION OF COM RAM 2 3 SD 2 ROM based BASIC SD2 is active when SHARP BASIC is executed via ROM MAIN CI U MS l H MSO 0 L SUB CPU MA3 RAM BANK MAI SELECT MAI MAO FFFF cooo 4000 im 0000 MO2 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 I I I RAMA RAMB 4 3 2 ROM B ROMA 0 1 1 2 3 4 ROMC ROMU ROM ROM2 0 0 0 M O 0 0 1 1 0 M O O 0 1 0 1 0 0 1 I 0 1 l 0 1 1...

Page 12: ... I I I I I I I I I lüftaJx RAMB RAMC RAM x 1 2 3 4 1 2 3 4 1 2 3 4 3_ L 2 V 0 RAJt SP RAM SC V RAM SB KOMo RAMA ROMl ROM2 KOW3 ROM4 ROM BAS 1L u S WfOOM Ut C ROM 1 Pl ROM 02 0 0 0 0 l 1 1 BANK M01 0 0 1 1 0 0 1 SELECT MOO 0 1 0 1 0 I 0 1 Bank select MAO MA3 is effective for memory area COOOH FFFFH 2 Bank select MOO MO2 is effective for memory area 2000H 3FFFH Operational description The state of t...

Page 13: ...SI MEMORY MAPPER 0 o O 200 4 O Sl BUS DK1VKR B CPU 80A A B U CTRL AS m P l 1 r r FKER II 1 1 T RAM 64KB 2 1 1 1 MI XH MDL IPLEXER pou OPTION U_ m MPXK COMMON RAM 2KB 1 ROM BASI C 1 S2KB 1 or KBX4 1 L iV F K 76 ROM IPL 1 RAM or ROM 8KB 8KB 1 1 r RECEIVER L LL MFD i o 1 1 OPTION f P I I SLOT1 SI OTZ SLOT3 SLOT 4 n T 1 ON MZIUO yinni i OK H n n V V T PRINTER l K J l ...

Page 14: ...1 1 0 0 0 X X t O Q 1 X X t O t O X X 1 1 1 0 1 1 X X 1 1 1 1 Q O X X 1 1 1 1 0 1 X X 1 1 1 1 1 0 X X 1 1 1 1 1 1 X X HEX 00 01 DE DF EO E3 E4 E 7 E8 EB EC EF FO F3 F4 F7 F8 F B FC F F NOT USE NOT USE SFDC UPD765 IOSF INTR NOT USE MFDC UPD765 IOMF IOAB MEMORY MAPPER SPD interface FDC chip select AO used for RD and WR A1 is don t care SPD interface I O port and DMAC chip select Interrupt signal fro...

Page 15: ...nication betweenCPU s 0001 S01 8251 8251 SIO Chip Select ASO is used for data control selection AS1 AS2 and ASS are don t care 0010 S02 8253 8253 counter chip Select ASO and AS1 are used for Programming during write AS2 and ASSare don t care 0011 S03 8255 8255 PIO Chip select ASO and AS1 are used for port control selection AS2 and ASSare don t care 0100 S04 input port Select 8 bit input port Used ...

Page 16: ... diagram ADDRESS BUS J AO l 13 14 1S CÜAB CONTROL BUS MERQ RFSH RD DATA BUS DO D7 oc INTB WAITB SYSR A15 A14 AI3 AI AO COAB MREQB RFSH Memory A 15 AI4 RB GAB 1 0 PORT LOGIC L L 1 WAIT TIMING GENERATOR CLK TORESET INTERRUPT PRIORITY ENCORDER I NTFI 19 ...

Page 17: ...d Parameter to the sub CPU or reads the message Status from the sub CPU Sub CPU Request Address signal to the main CPUdynamic RAM The main CPU addresssignals A13 A 15 merged in the memory mapping logic Circuit to produce AR13 AR15 This is means by which the 4 basic and CP M memory maps are made along with MS1 and MSO BASIC interpreter 32KB mask ROM chip Select signal Valid when SD2 is active Sharp...

Page 18: ...terrupt from Floppy Interrupt input from the sub CPU Interrupt from No 0 Interrupt input from slot 1 or 2 Interrupt from No 1 2 Memory reguest signal from the main CPU Memory Request Write signal from the main CPU Write Interrupt input from slot 3 or 4 Interrupt from No 3 4 Input from the FDD Floppy Disk Drive assignment dip switch A No 1 See the dip switch description provided separately Section ...

Page 19: ...ress Select Signal for 8KB area allocated to slot 1 Valid when SD2 is active ROM based BASIC and SD3 RAM based BASIC ROM 1 Ground 5V supply Select signal for 8KB area allocated to slot 2 or 3 Valid when SD2 is active ROM based BASIC and SD3 RAM based BASIC ROM2 3 Read signal from the main CPU Read EAIT signal generation Clock Clock Select signal for 8KB area allocated to slot 4 Valid when SD2 or S...

Page 20: ...errupt Status 1 All Output Signals are reset to Iow level upon power on l except for SRBQ that goes high 2 Noted with astar mark 6 are Input Output Signals and rest of others are processed in the LSI 1 I O port Output of ME1 and ME2 uses the memory at the addresses ME2 8000 BFFF ME1 4000 7FFF When ME1 and ME2 are in high state RSAB RASA is inhibited during memory addresses in RAM A that correspond...

Page 21: ...evel that inputs 1B 4B are enabled by sub CPU If A13 thru A15 were to be at Iow level the Output YO of the LS139 becomes Iow level so that the Output 3Y of the LS147 or CE of the ROM IPL should be at Iow level Should SRD SMRQ be at Iow lebel äs well the Output 2Y of the LS157 or 51 of the ROM IPL turnde to Iow lebel to read the ROM IPL Though the sub CPU can access an address ränge of 0000 to 1FFF...

Page 22: ...olors Programmable for each Character 640 x 400 dots B W one frame Color designation for each Character 640 x 400 dots B W three frames Color designation possible for each Character Color one frame Use of medium resolution CRT 8x8 dots Blink revers Programmable for each Character 640 x 200 dots B W Two frames Color designation possible for each Character 640 x 200 dots B W six frames Color designa...

Page 23: ... 14 80 x 25 80 x 20 40 x 25 40 x 20 By Character t t O X 3KB 1 frame t t Graphics option Color 640 x 400 By Character By dot 32KB I 96KB II No frame 1 frame 1 frame One Character screen against one graphic screen One B W Character screen against three graphic screens One color Character screen against one graphic screen Medium resolution CRT 640 x 200 dots mode Green monitor Characters ASCII 8 x 8...

Page 24: ... 640 dot 400 dot 200 dot Dot pitch Horizontal Vertical 1 1 Dot pitch Horizontal Vertical 1 2 W White Three basic colors 4 Attribute AT1 AT2 ATS AT4 B W Vertical line Horizontal line Reverse Blink Color B R G Blink Designated for each Chara cter Line and Character rr üy exist in the same element Line may also be dis played on the 80 charac ters x 25 lines screen 5 Screen overlay It will be possible...

Page 25: ...VRAM Displays on CRT1 the red elements contained in the VRAM Displays on CRT1 the green elements contained in the VRAM Displays on CRT2 the blue elements contained in the VRAM Displays on CRT2 the red elements contained in the VRAM Displays on CRT2 the green elements contained in the VRAM Choice of background Color display Color mode Border color mode in effect Defines the data size for the graphi...

Page 26: ...o o o o Refer to ROM address and data code on separate Information Model 3500 Address Data 1000 00 1001 10 1002 10 1003 28 1004 28 1005 44 1006 44 1007 7C 1008 7C 1009 44 100A 44 100B 44 100C 44 100D 00 100E 00 100F 00 8 Element structure Character structure and line Element structure Character structure and line Character pattern area Line area X Area where pattern and line are overload 640x200 d...

Page 27: ...of 25 line displaying of the PC 3200 vertically adjacent graphic symbols do not joint But they will joint with the Model 3500 Model 3200 Model 3500 2 No line will be displayed for the medium resolution CRT 640 x 200 dot It is possible to display line on the high resolution CRT compatible to line the utilizing program of the Model 3200 4 2 Video RAM 1 Structure of VRAM GDC1 for Character GDC2 for g...

Page 28: ...ther empty or Füll and can be accessed by 3 Structure of Character VRAM 1 When read write from GDC 07 FF 0000 refreshing during the display period Number of characters that can be read write within one raster in any mode A B A 2KX8 ASCI I 8bi t 30 Di B 2KX4 Attribute 4bi t ö U l 1 A S C l K S b i t i i _ __ _ _ i l 1 2 b i t i DO Dl D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 L Blink Vertical line R Horizontal ...

Page 29: ...High byte __ i R i 16K RASA RAS A14 A15 RASB RAS A14 A15 RASC RAS A14 A15 0 0 0 0 3FFF 4000 7FF F 8000 BFFF 2 Display mode A14 and A15 are not valid and RASA RASB RASC are selected together By the DBIN signal from GDC 2 08 16 signal isgener ated by CSP 2 The signal of 08 16 Select after P 5 conversion for RAMA RAM B Output signal then Output to V B by Serial signal or sprit the signal to VB and VR...

Page 30: ...signated tor each Character I6K Video 6K 0 0 0 0 X i 16b t B W 3 frames Color 1 frame 8FFF B R G 16K iL 0000 r 16K 4 l i r 16bit 16bit 16bit X e s T X Y 1 2 Dot Clock ÖD 2XCCLK Horizontal display time HFP HS HBP Vertical display time VFP VS VBP GDC 1 SOdigits Character display 40 digits 16MHz 8MHz 4MHz 2MHz 40 js 7 as 6 JS 10n 1 2 6ms 1 2ms 1 ms 1 8ms GDC 2 8 bits 16MHz 4MHz 14 Chr 12Chr tREFO Sms...

Page 31: ... Vercial synchronization frequency fV 47 3Hz 3 Total rasters 441 rasters 4 Rasters used 400 rasters 5 Display dots 640 x 400 dots 6 Dot Clock 19 66MHz 7 Timing Video Positive 9 HS VS and VIDEO Signals are supplied from the LS type TTL IC totem pole 6 Setup of GCD master slave 1 Master slave setup by combination Character GDC Graphic GDC Without VRAM PWB 8 bit structure 48K byte 200 rasters 16 bit ...

Page 32: ...nal calied CH48 is provided apart from the I O port l 08 16 I O port inside CSP1andCSP2 7 Graphic V RAM Address Relation between VRAM address and screen 640 x 200 dots 8 bit structure t m m Graphic address map for 200 rasters L OO l IV U 0000 0001 0002 0003 0050 0051 OOAO OOKO 3F30 00 tl D09I 31 K 16 bit structure Graphic address map for 400 rasters CRTC block diagram Color graphic VRAM PWB opnnn ...

Page 33: ......

Page 34: ...LS166 shift out Clock Used to latch the image data in CSP1 Attribute data input from the 2114A 1 attribute RAM f AT 2 Horizontal line R AT 3 Reverse G AT 4 Blink J Input of Character display data signal 0V supply Input of display timing signal supplied from the CSP 2 BLINK signal from the GDC2 is delayed by two flipflop intervals in the CSP 2 to creat this signal VIDEO Output to CRT2 Character CG ...

Page 35: ...e 4 3 5 3 CSR j Merge 4 T 1 Circuit JO CO I r r fJ M x y_ B VL Character R HL g r e Circuit 1 _ Cursor erase Circuit CSR 2D J 1 ÜSPT y O f Y Tr 1 n H RXHL 5 C RV i QJ o O ü COLOR O T EAT2 1 KAT2 W 57 r i S unter nal generato 1 1 40 40 81 shift r X er i 03 r 1 i n M 1 L i 80 4 diait Circuit r r B W attribute merge Circuit Cursor Blii T o is0 S 5 o J3 sll _i X 5 1 1 m H Ai T MM v_ Border L backgroun...

Page 36: ...rd and 16 bit word select Signal 8 bit word chosen with LDA OOH OUT 5D and 16 bit word is chosen with LDA 01 H OUTiSD Memory control Signal RAS from GDC1 Used to create CGOE SL1 in CSP 2 Memory control Signal RAS from CDC3 Used to create SL2 LOAD RASA RASC CAS FS DBIA DBIC DSP2 in CSP 2 Address bus input from the sub CPU ASS AB3 Chip select OUT 5X of the I O port in CSP 2 Data bus input from the s...

Page 37: ...UMN ADDRESS SELECT Signal Line address selection 6V supply CSP 2 Block Diagram VW R O HAS2 C ÜB 2 C r z ft 32 MHz i PR Hexadecimel counter 200 Raster Clock se ect 39 32 MHz ClfCuit 400 Raster C rasters K I O L 1 08 16 so 1 C n F D S li o 8 16 bltt 0 i r Os CK O O 5 Select Circuit SRAM CG control signai generator C i l J CQ ä S GDC1 Character L diiplay clock generator GDC2 graphic displav Clock gen...

Page 38: ...ion of the DISP START command Memory control signal sent to ihe image memory from the GDC In the dynamic RAM mode it is used ästhe reference signal of RAS When at high level used äs the timing signal by which the address signal is latched Row Address Strobe DMA request Output which is connected with the DRQ input of the DMA Controller is Output by the following two commands 1 DREQE DMA request wri...

Page 39: ...ss Data bus13 15 Line Count 0 2 Provides the following functions based on the operational mode of the GDC graphtc display mode 0 Character display mode 1 1 Graphic display mode Image memory address Output 2 Character display mode 1 Line counter Output 3 Character display mode 0 Attribute blinking timing signal and external line counter clear Signal Address 16 Line Count 3 Attribute Blink Clear Lir...

Page 40: ...ters ASCII Character Structure of the 200 raster CRT ASCII Character Structure of the 400 raster CRT Circuit description Purpose The Character genrerator CG incorporates all Charactercodes used by the 200 raster video display unit of the YX 3500 and by the 400 raster video display unit of the YX 3500 The CG address select Circuit is therefore used to select those modes Operational description 1 Wh...

Page 41: ... The above Circuit shoud be used to compare with the table description GDC 1 Character GDC 2 graphicl Without VRAM PWB 8 bit structure 0816 01 48KB 200 raster 16 bit structure 0816 1 48 96KB 400 rasters CH48 0 40 digit GDC1 Character is the master GDC1 GDC1 CH48 1 80 digit GDC1 GDC 1 GDC2 Graphic The master GDC must be set äs indicated above Oprational example If it was set to 80 digit 16 bit word...

Page 42: ... half of attribute 10000 07PF BLNK Erasesignal H SYNC TU BLANK Period that the GDC is enabied to read write and draw graphic data Circuit description With respect to GCD1 the assignment during read write of the Character VIDEO ROM is per the table below The Character VRAM Select Circuit is provided to aecomplisb this function L AK11 l uw 0 0 0 0 6 1 1 6 2 K x 8 V K AM Latter half of attribute Firs...

Page 43: ...00 1 Read write via the 16 byte FIFO 2 Read write of V RAM in the DMA mode without Intervention of the FIFO Outline of the read wriie data via the FIFO NO YES Set GDC command code YES Set parameter for the command YES Set parameter for the command Method used to give a command to the GDC Command must be given to the GDC in the same manner On next page is the program of the above flowchart 48 ...

Page 44: ...ter not sent FIFO Empty PARAMETER GDC Return when all Parameters were sent RET Exarnple of graphic drawing by GDC 1 Dot display 0000 0028 0001 0027 VRAM 16 bit structure Example to display a dot on the fourth bit of the address CSRW C 49H COMMAND CODE P1 01H Low order one byte of the ab solute address P2 OOH High order one byte of the ab solute address P3 30H Dotaddress dAD WRITE C 23H COMMAND COD...

Page 45: ...D INC LD INC LD INC LD LD LD LD HL HL L H L L H L L HL L H L L HL 1 l C B HL 5 0 0 0 H 49H 01H OOH 30H 23H 6CH 60H 4 H 5 0 0 0 H CSRWdata 5000 49 H 5001 01 H 5002 00 H 5003 30 H 5004 23 H WRITE data 5005 6CH VECTE data C 60H port address during graphic draw B Byte size CS RW data HL Topaddress of theCSRW data CALL GDC Command par meter of CSRW GDC LD LD LD C 6 0 H B 1H HL 5 0 0 4 H B Byte size of ...

Page 46: ...CTE c Pl P2 P3 C Pl P2 C Pl P2 P3 P4 P5 P6 P7 P8 P9 C C 49H 28H OOH 20H 78H FF FF 4CH OAH 78H 02H 88H FI H 1 OH FBH OOH OOH 23H 6CH EAÜ L H dAÜ Kind of line solid line Drawing direction IAX l 2 AY l I A X l 2 l A Y l 2 IAX l 2 AY l Explanation Specify the kind of line by TEXTW using C for command code and P for parameter and specify the line drawing direction using VECTW and above four values usin...

Page 47: ...nclature Floppy disks called by different names dependng on the manufacturer fo Floppy media or simply äsmedia jo Diskette o Floppy disk 2 Types of media Four types are used at present depending on their storagecapacity fo Single sided double density floppy disk 1 o Double sided double density floppy disk 2D Smgle sided media Index detect hole Double sided media index detect hole Front side Head 1...

Page 48: ...quires that a clock bit that This method is called the freqency modulation FM precede the data 1 0 0 1 0 n n n n n n n n C D C D C D C D C D C C clock D data Waveforms of data Written or read in the FM mode are shown below l 4 S Write data WO Write current Residual magnetic flux on the media Read waveform Differentiale waveform Shaped waveform Read data RD r C D C D C U C D C D C D n n n n n n n n...

Page 49: ...that follows Data that precedes The clock pulse C will be eliminated in above Illustra tion äs there is no data preceding or following the clock Because the data rate is 2 Js for this method it is possible to obtain twice the density of the FM method NOTE Three types of write data cycles Ip 3 s 4 is are used The read write waveform is identical to FM method 6 Media recording formal Media is format...

Page 50: ...on or to partition data area Keep the difference between formatting and initializing in mind Note 2 Unless formatting has been done on a properly adjusted floppy disk drive unit an erroe may occur on another floppy disk drive unit 8 Data write procedure Described next is the procedure to write data on the FD 1 The head is moved over the track to be Written 2 3 4 The head is loaded l D section is r...

Page 51: ...M Z 3500 5 3 MFD Interface block diagram MOTOR ON 56 ...

Page 52: ...TA O WINDOW GJo 0 WCLK i O J S vV 0 KM M K R S S E R I A L 1 STERFACE CONTROLLER n UA R r AT 4 DR 1VE CONTHO1 LER A W 1NPUT PORT OUTPUT PORT kf ADY M KT 2S i DF Fl T TRKO 1 M t M K SEEK HiK D S f t F LCT DI R FLTR STEP RESET RD WR CS AO DBO 7 DRQ DACK TC INDEX INT 0 GND WCLK WINDOW RDATA SYNC WE Reset Read Write Chip Select AO Data Bus DMA Request DMA Acknowledge Terminal Count Index Interrupt Req...

Page 53: ...the VFO Circuit When 1 it permits reading Operation When 0 it prohibits readingOperation Signal used to discriminate the read write signal from the seek signal that used for drive unit interfacing signal When 0 it indicates RW When 1 it indicates Signal used to load the read write head Signal used to select head 0 and head 1 for the double sided floppy disk drive unit When 0 it selects head 0 When...

Page 54: ...1 MF recording method 1 Clock bit indicatesa bit cell 2 Data bit is placed in a middle of a bit cell SeeFig 1 n 0 n 1 1 i 1 0 0 i 0 i 0 n MFM recording method As seen from the above Illustration bit density of the MFM recording method is twice the FM recording method In other words data density of the MFM recording method doubles that of the FM recording method For the Model 3500 only side 0 of tr...

Page 55: ...e 1110 E will be set to the LS163 so that the output is issued 125ns earier than not changed The QB Output however will be supplied for a period of two clock cycles 5 8 Media detection Insertion of a media on the MFD is detected via the signal INDEX from the MFD Since it takes 200ms for the media to make a füll turn NO MEDIA is detected signal INDEX does not appear within 200ms Set the counter to ...

Page 56: ...n the Output vaveform is observed after writing a single pluse on the floppy disk the waveform show in a appears Shown in b is two pluses of 4 is interval Deviation in the peak point iscalled peak shift Since pluse intervals of the MFD in actual Operation are 4 is BAIS and 8fis the largest shift takes place when a pluse appears 8 Js before or after 4 is äs shown in c 5 10 VFO Circuit 1 Purpose Str...

Page 57: ...owing capabilities 1 Two modes MFM and FM 2 The VFO Circuit Operation is suspended during the SYNC field located before the ID field and data field 3 After suspention the VFO Circuit will synchronize with the read data timing is affected by a speed change in the FDD Fluctuations in an individual bit that may be seen peak shift are ignored VFO Circuit 4 5V READ DATA 62 ...

Page 58: ...MFM Mode L Nomal STD Eary O n n Delay 63 ...

Page 59: ...M Z 3500 FM mode Timing chart A 4M B QA C QB D QC WINDOW E F L i r i i i n r i i i i Normal Advanced O P F L Q O P Delayed L K Q O P _T Does not trace 51jus 64 ...

Page 60: ...ormation See Fig 1 BOOT BOOT BOOT C5 D9 D4 Cl D7 40 _ BLANK MEDIA 00 00 00 00 ____ 40 00 E5 D6 D3 Fl E2 C8 Cl D9 D7 40 40 D4 40ononeside 40 Fl I MAP Nine sectors for the media of 34 tracks Area 10thsector es also a MAP area for the media of 40 tracks j MAP FF J Area FF FF E5 E5 E5 E5 E l c i i 1 L T r ä i c 1 65 ...

Page 61: ...reverse side No of data transfers INT IOCScapacity 1k 1 N SIDE 0 track 8 sector 78 F Volume name FF FF 10 11 t f II 18 IF FF FF FF FF t Diskette Type 3Ck No 2 4 SH DD Mini 20 SC For FLOAD command Track No 1 C DH DD Mini Error Mep Bad Treck E DHXDKStandard 3D 7F FF FF 2C Fail name 8 bytes Expander Volume name FF No ALOAD command 80 File specification only 01 With Operand 3 bytes 8 bytes Drive NO Ch...

Page 62: ...H FFH FEH FFH FFH 129 130 131 151 152 153 FFH I 7H FFH FFH FFH 128 blocks are controlled by one sector OOH 7FH 80H Endof link FEH Links to next map and the starting block number Indicates the bytePosition from the top of directory 25 261 27 28 29 30 31 fSÜ 02 0l FF FF FF FF FF MAP Na Block NO Starting block number directory 67 ...

Page 63: ...3 15 sector 3 Track 1 See 0 AA l resents t em med SECTO RNUM BER t Drive un specifica he 2 sector 4 6 1 block J 1 block 14 16 sector tor 1 Information CP M 5 10 15 SFCTO DATAT TRACK SIDE SECTOR N 5 NUN Po tJil TRACK SIDE SECTOR N BER MBER t Load address Start address tion T r r T 20 50 51 TRACK SECTO SECTü BER BER j Indicates the end C TIR mrc SIDE _ 0 Single density front Track 0 1 Double density...

Page 64: ...t even or odd parity 8251ACor82S3C 5 Programmable Interval Timer 6 2 Data transmission format 2 21 22 23 24 25 26 7 bit with parity v v 1 Start bit Data bit 7 bits Parity bit Stop bit 1 or 2 bits 7 bit without parity v _ Start bit Data bit 7 bits Stop bit 8 bit with parity 8 bit without parity y 5tart bit s Start bit Data bit 8 bits Parity bit Stop bit 1 or 2 bits _ _ Data bit 8 bits Stop bit 1 or...

Page 65: ...ld not be set high when the echo back function is selected for the host Computer Polarity is inverted 6 5 8251AC controls There are two control words for the 8251AC 1 Mode instruction Defining general operational para meters such äsunit stop bit etc 2 Command instruction Defining Status words used for actual Operation such ässend receive enable etc 1 Definition of generation operationalparameters ...

Page 66: ...R X E N T X E N 8251 AC 8251 AC L TfS Set counter 200ms Stop Output data to 8251AC ERROR101 The 8251 send data when CTS goeslow The 8251AC would not Output unless CTS goes low Therefore the state of CTS will be checked when the DUHer l becomes empty ERROK101 73 ...

Page 67: ...a input disable Read one data Clears thedata before the start of the receive command Command instruction RXEN DTR TXEN 8251 AC 8251 AC Data input enabied Data Output enabied echo back selected Waits for NMI by the RXRDYSignal Resets error by setin DTR high Command instruction EK 8251 AC ERROR ERROR 74 ...

Page 68: ...urned off SW7 ON Causes an error if set high during data Output SW7 OFF Causes an error if set Iow during data Output 6 7 Description of LSI s 1 UPD8251AC Programmable Communication Interface The UPD8251A is a USART Universal Synchronous Asynchronous Receiver Transmitter that was specifical ly designed for data communication The USART receives parallel data from the CPU and converts it into Serial...

Page 69: ...o be used for a wide ränge of microcomputer System timing control Features Z 80 compatible Three sets of 16 bit counters DC 4MHz of count rate Programmable six operational modes and timer duration Choice of binary counter BCD counter N channel MOS input output TTL compatible Single 5Vsupply 24 pin DI P Intel 8253 5 compatible Pin configuration Top View VCC JRTJ 3CS 3A1 JAO 3CLK2 JOUT2 5GATE2 3CLK1...

Page 70: ...ITTER CLOCK RECEIVE DATA RECEIVER READY RECEIVE CLOCK READY CS PO MPER SUT ER CD RD OUT 0 of 8253 SD To siib CPU of 8253 OUT 8253 8253 Chip address 0010 xxxx I N UXH O U T f l 2 X CLKO GATEO OUTO CLK1 GATE1 OUT1 CLK2 GATE2 OUT2 IN IN OUT IN IN OUT IN IN OUT 2 45MHZ Vcc To TXC RXC of the 8251 2 45MHZ From OUT2 MUSIC 2 45MHZ Vcc To GATE 1 INTO TO MAIN FROM SUB c POWER ON RESET SOO S I W IORQ WR O f ...

Page 71: ...0 PDTR A bo ve pin numbers are of the model 3500 main unit Pin No 1 3 5 7 9 11 13 15 17 19 21 23 25 27 Signal name STROB DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 DATA 7 DATA 8 ACK BUSY PE PDTR SYSRES IN OUT PRINTER PRINTER PRINTER PRINTER PRINTER PRINTER PRINTER Function Data is transferedto printer when STROB is high Data Output to the printer Indicates the end of Character input or function inp...

Page 72: ...al äs it uses Interrupt for key processing and RS232C input the ACK signal is latched by means of the DBF pin function BUSY ACK OBF 8255 A 1 PC 7 DATA STROBE 1 U c f MIN 1 J 1 1 1 1 l t l I I V 1 1 1 l l r PRINTER MZ 1P02 MZ 1P03CE 330P 331P 332P Broken line in the above figure represents timing for the CE 330Pand331P For detail of timing refer to Manual provided with Printer 7 5 General descripti...

Page 73: ...2 PB1 PBO Output OBF Output INTR Output DATA8 I ATA7 DAT A6 DATA5 DATA4 DATA3 DATA2 DATA l ACK T S ET ACK STROBE J MUS IC sustain NOT USE ACKC STC DC P M SRDY CLK Printer Din C2 Cl CO STRB Keyboard CG seleclion Sub CPU READY Clock INPUT PORTC 74LS244 74LS244 port address 0100 xxxx IN OUT 4X CDS73 CDS6D CDS5D CDS3D CDS2D CDS1 CDSOD HLT KEY STK i DK J PDTR PE BUSY Reads the 8255 OBF PC7 Output or ti...

Page 74: ... 2 Clock timing READ HOLD READ SH1FTmode y mode mode j mode Cn CO C2 0 X HOLD Tsode WRITE HOLD mode mode Tens digit of seconds SHIFT mode Tens digit of month SHIFT mode Cn CO C2 0 STB Ones digit of seconds DI N Don tcare X A X t CLK i I OUT J_ Tens digit of seconds SET i HOLD mode mode Don t care XZHZXZ1 Tens digit of month 81 ...

Page 75: ... 40 bit S R is preset to the time counter Data in the time counter is read to the 40 bit S R DOUT 1Hz LSB Output of LSB LSB Output LSB Output Data Shift Not possible Possible Not possible Not possible Note Data retention Shifts in synchronization with the clock Input Output format Example In the case of 10 o clock 25 minutes 49 seconds July 30th SB MSB g 4 5 2 0 1 0 3 7 L Seconds L Minutes L Hours...

Page 76: ...S X S 0 rvj ro Q t ir 1 5 1 4 1 2 2 4 9 1 5 1 8 1 3 cc 1 vcc_ l 1 777 A C458 T S JT r 5 i T CLOCK GENERATER 2 45076 MHz ni Vj T A 711 9 Sr X T Xj 4 r Jl ii n ii 7 il Vc T VOICE SPKR Music Output waveform TonalSignal OUT1 Sustain PC4 2SC458 emitter 2SC458 collector Speaker Output GETE1 l 83 ...

Page 77: ...lution color CRT 14 CRT tut stand 12 CRT tut stand Light pen 80 character printe Color injket printer 80 character printer 136 character printer Optional MFD drive unit Plotter Optional MFD drive unit Optional MFD drive unit single deck Graphic board MZ 1E01 RS232C 1 F 1E02 GP I O 1E03 SPD 1 F 1F05 SFDunit 1R06 RAM 2 Expansion unit Signal assignment by slot Main CPU bus line BASIC SFDCONTROL VOICE...

Page 78: ...00 CG will be assignedwhen the 200 raster CRT is in use 2000 CG will be assigned when the 200 raster CRT is in use 48 pin of MMR ToCTS DSR of the 8251 To CTS of the 8251 54 pin of MMR FDD P M signal To A3 CG N C Dip Switches A and B located on the PWB are used for servicing the M FD or for other machine service and there fore the user is not supposed to use these switches In addition these switch ...

Page 79: ...machines this us the single sided minifloppy disk drive Switches aresetin this manner before shipment of oc n PPTK H machines that use the double sided minifloppy UrSiJJ vX JSii disk drive V M iJb4U Y Switches are set in this manner when the SH is used for the optional MFD Switches are set in this manner when the DH is used for the optional MFD Test mode 1 Test mode 2 Individual CPU PWBfest f Can ...

Page 80: ...e at both ends of the over current detector resistor R1 which in turn causes to increase the Q3 collector current for there arises larger voltage difference between the emitter and base of the transistor Q3 This makes the gate voltage of the thyris tor increased owing to activation of SR With activation of SR it makes the oscillator voltage dropped to the GND level at the point a to stop oscillati...

Page 81: ...tching regulator V V Q5 5V or Switching regulator and constant voltage control Circuit JUUUL 25KHz Oscillator Circuit VR is the 5V or 12V adjusting VR D3 isprovided to discharge current from Cj after power off 88 ...

Page 82: ...smoothed voltage through the capacitor C1 and the coil L2 The Circuit composed of D4 and VR1 is the reference voltage for the 5 or 12V supply which is used to control the emitter current flowing to the transistor Q9 The current supplied from Q9 is used to create Tr3 inactive by the delayed C1 and C2 voltages which supplied from Tr1 R2 VR1 D3 It goes high with deactivation of Tr3 3 Alarm Circuit Al...

Page 83: ...conjunction with the CTRL key L DEFIB DEF10B DEF1B DBF10B 6 Handling of functional Symbols and graphic Symbols See the code table 7 Useof the CTRL key to discriminate RUN and CONT of the DEB key Push the DEB in conjunction with the CTRL key to Start running 8 Handling of special codes COPYcommand CTRL 1 ten key ESCape CTRL BRK CTRL 9 PRO OP Sent to the CPU after power on and when PRO OP is changed...

Page 84: ... n n n 15ms n n n DATA OUT Two key entry Key 1 VVL Key 2 STROBE n n n n n RET Jl 5 5ms X 5 5ms M 5ms M 15ms M 15ms n n n n n n n n n DATA 1 OUT DATA 2 OUT 10 3 Key serial transmission procedure 1 Dataformat Key CPU i i i i r i 27 26 25 24 23 22 2 2 DATA Parity All nine bits Command Key AM 4 bits 22 2 2 Parity 91 ...

Page 85: ...troller accepts it Unless the ACK signal was detected the same data is sent again assuming a transmission error Case when the error data link sub CPU not enable to receive data properly is established 1 When parity error is found after the check sum test 2 When the sub CPUis in execution of the NMI routine or when NMI is applied during data transfsr 3 When an error is detected in the couting of St...

Page 86: ...MZ g 500 10 4 Keyboard Controller basic flow Power ON 93 ...

Page 87: ...used to activate the keytop embeded LED 32 pin Alphabets and Symbols LOCK 33 and 34 are not used Not used Keyboard type idemifier pin Keyboard type is identified by means of KSO KS1 KS2 of KUC1 an KUS2 whether it is GND or NC Acknowledge input from the CPU ACK O Sent only when the CPU receives a correct data 5V supply 11 SELF CHECK FUNCTIONS The 3500 performs self check lest during initial program...

Page 88: ...rt executing the test Procedure 1 Set dip Switches on of the 4 bit unit located in middle of the front side of the board äsillustrated at the right No POSITION 1 OFF 2 ON 3 ON 4 ON j 2 Set dip switches on of the 2 bit unit located on the front side of the board 3 Insert the media into a slot of any diskette drive unit 4 Turn the power on 5 Load the program from the specified track and sector to st...

Page 89: ...ide Test items Memory VRAM GDC peripheral clock Speaker printer Interface light pen and RS232C Interface GO NO GO of the test must be confirmed on the Video screen Moving from test to test is done by depressing the HALT key Procedure 1 Turn OFF all dip switch of the 4 bits unit located in the middle of the front side of the board and turnOFF all dip Switches of the 2 bits unit 2 Set the system dip...

Page 90: ...en by space Test end 1 Normal VR OK 2 Abnormal VR ER 3 CRT inter face test Performance of the CRT is tested To move into each test Phase push the HALT switch Test No 1 No 8 test the 400 raster CRT and test No 9 No 16 test the 200 rasters CRT Procedure and display TestNo 1 Confirm all patterns on the display screen of 40 digitsand 20 lines Test No 2 Confirm all patterns on the display screen of 80 ...

Page 91: ...5 are tested Dispalyl 1 Normal test ending PR OK 2 Abnormal test ending PR ER 6 Light pen Interface test Performance of light pen interface signal lines and the action of the GDC are tested Display On the upper left corner of the screen is displayed Character and line 1 Normal test ending LP OK 2 Abnormal test ending LP ER 7 RS232C interface test Performance of RS232C interface signal lines and th...

Page 92: ... MAIN CPU CHECKER FLOW CHART 1 2 MZ 3500 MAIN CUP A CHECKEfiSTAHT J Loaid th teil p ogiafn l Vriie 66 r d Dt nTrackiO 20 Ml39 NOTE Includ SEEK etrof and RECALIBRANTE fror NOTE Includ SEEK erfo nd RECALIBRATE 99 ...

Page 93: ...M Z 3500 MAIN CPU CHECKER FLOW CHART 1 2 Option RAM read wriie check N Change bank of the Option RAM Error indicated on display c HALT 100 ...

Page 94: ...M 7 3500 SUB CPU CHECKER FLOW CHART 1 3 SUB CPU CHECKER START l RAM bas d mod l Y Read wfiie rheck öl the 1OCS RAM Add up all figures n The OCS RAM 101 ...

Page 95: ...d test 1 As the power is turned on with the DEB in depres sion it goes into the keyboard self test mode 2 Depress key in a given sequence If key is depressed in a correct sequence it makes the alpha symbol LOCK LED activated each time a key is pushed If the key was pushed in a wrong sequence or when a failure is met in the key it makes the LED blinked 3 It returns to the normal mode upon completio...

Page 96: ...Jumplo400EH ROM R AM fest Select memory location SUM tPL START Check MFD Index tignal Contents of Parameter secior 1 Kind of MFD Singfe side double dencity or double side double dencity 2 Track and sector where iOCS is stored Loadhiq j and truch Number of sectors Note The sub foader is coniained in the leadingsector 103 ...

Page 97: ...to shared RAM 8000H F800H LOAD BOOT NO SEEK READ ERROR c I O SYSTEM LOAD ERROR transfer HALT CPU STOP ERROR BOOT Program used to Start the System I O SYSTEM LOAD ERROR transfer HALT CPU STOP LOAD BOOT SSEK READ C JUMP BOOT ADDRESS Position of boostrap program on the media Sector 2 thru 5 of Track 0 ERROR C BOOTERROR on disp HALT CPU STOP 104 ...

Page 98: ...k ROM sum Initial GDCand check G VRAM Set the custom LSt CSPI and CSP2 control boards Initialize GDC again C GDC G GDC commdnd transfer b IPL ROM is roke is indicated on dispJay HALT l CUP STOP l Transfer sub CPU IOCS rom the shared RAM JUMP SU8IOCS J The main CPU v ill perforr media u insetted retnals unnt the rnat 105 ...

Page 99: ...ÜJLULiJL JLiJLLlLlJljjLJLlLlJ IC AI 2V 1A2 2V3 IA3 2Y2 IA 2Y1 CN I üJ LDLÜ U LlJ LL ÜJ IA 1B IY 2A 2B 2Y GNU VCC n i 74 IS 04 6A 6Y SA 5Y A 4Y LU LU LU LULLT LU LU IA IY 2A 2Y 1A 3Y GM LU LU LU LU LULU LU l A l B IY 2A 2 B 2Y GNU VCC IC IY 3C 3B SA SY R R R R R R R TJHJ IJJÜJ LULULJ IA IB 2A 2B 2C 2Y GNI 74 LS l 39 SELECT DATA OUTPUTS 2Yp zvi 2Y2 A I 1 i A A G A B G A B YO 1 1 Y YO Y Y YI Y2 Y Y2 ...

Page 100: ... m 55 7 3 l LJ L LJ LJ LÜLü U l ILl ICK 1PR 10 s GNU CLR ENABLE 2 J 20 l i CM 3 J 3 1 L I r i u ri ö H 1 u ö l J l L 1 W 0 1 O Ö s j n LULÜLULlJLLjLULlJLJ s 11 2D ENABLE va 3U 1U 4 1 1 S 4 7 4LS66 Vit H 4A IY H j A m rrn M R m LJ LLl Lü Lü LJ Lü U l H IV A h V M Lü Lü LD Lü Lü UJ Lü M SELECT IA 1B IY 2A 28 2Y CND V OUTPUT V Vu 4B A Y SB JA IV R r i r iR r i rn m LJ ÜÜ LU LÜ LU LU LU v l A IY A 2B ...

Page 101: ...MZ 35OO PARTS GUIDE LI ...

Page 102: ...4 0 P 0 8 0 0 0 X C P S D 4 0 P 1 2 0 0 0 P H O G 1 0 0 1 ACZ Z G F T A F 1 0 0 2 A C Z Z L H L D W 6 6 5 5 R C Z Z Q L U G L 0 0 0 6 U C Z Z X B P S D 3 0 P 3 0 K S O VR S PT 3 L B3 3 0 J L H L D W 6 6 5 5 R C Z Z P S L D M 1 0 0 3 A C Z Z T L A B Z 1 4 0 0 C C Z Z PRICE RANK A Y A E A E A B A A A C A A A C BM A L A C A C A A BG AM A X A E A Y A A BM A B A A A A A C A A A A A A A A A C A E A B A ...

Page 103: ...8 in ro N S O x UÜ S A y tf H ...

Page 104: ... Q C N W 1 0 0 7 A C Z Z X B P S D 3 0 P 1 0 0 0 0 X B P S D 4 0 P 0 8 K S O X N E S D 3 0 2 4 0 0 0 P H Ö G 1 0 0 2 A C Z Z X N E S 0 3 0 2 4 0 0 0 L H L D F 6 6 4 8 R C Z Z P C U S G 1 0 0 1 A C Z Z PRICE RANK A C A F A B A F A E A F A N A A A 0 A C A D A K AM AM AM A A A A A A A A A H A F A A A E A Q A X A A A A A A A C A A A B A A NEW MARK N N N N N N N N N N N N N N N N N N N PART RANK C C C ...

Page 105: ...CZ E Q C N C W 1 0 0 8 A C 0 1 Q C N C W 1 0 0 8 A C 0 2 QCNW 1 0 4 7 AC Z Z Q C N W 1 0 A 4 ACZ Z Q C N W 1 0 0 4 A C Z Z Q C N W 1 0 0 3 ACZ Z L H L D F 6 6 4 8 R C Z Z PRICE RANK AW A T A Z A Q A X A K A C AC A A A C A B A C A F AM AM AM A K A B NEW MARK N N N N N PART RANK C C C C C C C C C C C C C C C C C C D E S C R I P T I O N Connector Connector Connector Connector Connector Connector Conn...

Page 106: ...P A N X 1 0 4 M V C T Y P A 1 N X 1 0 4 M V C T Y P U 1 E X 1 0 3 M V H D D S 1 5 8 8 L 1 1 V H H M 4 7 2 1 1 4 1 VH HM6 1 1 6 P 3 1 V H L H 0 0 8 0 A 1 V H M 5 8 7 2 5 P 1 5 VH M 7 4 L S O O 1 VH M 7 4 L S 0 2 1 VH M 7 4 L S 0 3 1 V H M 7 4 L S 0 4 1 V H M 7 4 L S 0 8 1 V H M 7 4 L S 1 0 1 V H M 7 4 L S 1 2 5 1 V H M 7 4 L S 1 3 8 1 VH M 7 4 L S 1 3 9 VH M 7 4 L S 1 4 V H M 7 4 L S 1 5 7 VH M 7 4...

Page 107: ...o transistor GL3PR2 Resistor 1 4 W 330 J Resistor EX 110V 220V only 1 4W 47 5 Resistor 1 4W 5 Resistor 1 4W 100 5 Resistor 1 4W 1KO Resistor 1 4W 10KQ Resistor 1 4W 100K 5 Resistor Japan only 1 4W 2 2K 5 ResistorIl 4W 330 1 J Resistor 1 4W 3 3KD 5 Resistor 1 4W 33K Resistor 1 4 W 560 J Resistor 1 4W 6 8KO 5 I Resistor 1 4W 1 5KOJ Resistor 47 Resistor 1 4 W 680 J Resistor 1 4W 820 5 Resistor 1 4W 8...

Page 108: ... A A B A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A NEW MARK N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N A A N A E A A A A N N PART RANK B B B B B B B B B B B B B C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C ...

Page 109: ...MZ 3500 J MZ1K02 1K03 1K04 1K05 Key unit c 18 19 17 19 21 ...

Page 110: ... P A H A Q A E B S A A A A A A A A A A A B A C A A NEW MARK N N N N N PART RANK E C C C D C C C C C C C C C C B B B B B B B B B B B C C C C C C B C D E S C R I P T I O N PWB unit Packing cushion Packing case Screw Sealmg label Angle_ _ IC socket LSI socket Capacitor Capacitor Capacitor 16V 100 F Capacitor 16V 33 iF Capacitor 25V lOOj F Capacitor 50V 330pF Capacitor 12V O ljif Zener diode LSI RAM I...

Page 111: ...4 8 4 1 Q C Z Z Q C N C P 6 0 4 1 Q C Z Z Q C N C W 0 2 0 7 H C Z Z Q C N C W 1 00 1 A C Z Z Q C N C W 10 0 6 A C Z Z QCNCW1 0 0 7 A C Z Z QCNCW1 0 0 8 A C O 1 Q C N C W 1 0 0 8 A C 0 2 QCNW 1 00 1 A C Z Z Q C N W 1 0 0 2 A C Z Z Q C N W 1 0 0 3 A C Z Z Q C N W 1 0 0 4 A C Z Z Q C N W 1 0 0 7 A C Z Z QCNW 1 04 4A C Z Z QCNW 1 04 7A C Z Z Q L U G L 0 0 0 6 U C Z Z QP N 2 0 0 5 S C Z Z QPWBF 1 0 0 5...

Page 112: ... C C C C C C C C C C C C C C B B B B B PARTS CODE VH i HM4 7 2 1 1 4 1 VH i HM61 1 6 P 3 1 V H I L H 0 0 8 0 A 1 VH i M 5 K 4 1 1 6P 2 VH i M 5 8 7 25P 1 5 V H i M 7 4 L S O O 1 V H M 7 4 L S 0 2 1 VH I M 7 4 L S 0 3 1 VH I M 7 4 L S 0 4 1 VH i M 7 4 L S 0 8 l VH I M 7 4 L S 1 0 1 VH I M 7 4 L S 1 25 1 VHI M 7 4 L S 1 2 6 1 VH i M 7 4 L S 1 3 8 l VH I M 7 4 L S 1 3 9 1 VH I M 7 4 L S 1 4 1 VH I M ...

Page 113: ... C C C C C C C C C C C C C C C C C C C C C C C C C C C C c 1 PARTS CODE V R D S U 2 E Y 8 2 4J VRN RT2EK 1 02F V R N R T 2 E K 1 05F V R N R T 2 E K 1 2 3F VRN RT2EK222F VRN RT 2EK4 72F VRN RT2EK9 1 2F VRS PT3AB1 00 J n V R S P T 3 A B 1 02 J VRS PT3DB1 02 J VRS PT3DB1 52K VRS PT3DB680K VRS PT3LB330 J VSP0080P 608N VS2SA673 C 1 VS2SA673 D1 1 VS2SC4 58KC 1 X XBBSC26P04000 XBBSC30P06000 XBPSD30P06KS...

Page 114: ...118 6 118 6 120 6 121 6 123 6 39 6 40 6 116 6 38 6 119 6 41 6 124 6 122 9 51 9 51 9 51 PRICE RANK A C A C A G A N A C A C A C A C A C A F A C A C A C A C A C A C A C A Y A C A C AH A G A G A T A C A D A D A G A G A G A G A G A G A S A L A H AH A D A G A X A D A D A F A D AD AD A D A D A Y A P A H A E A D A D A D A D A E A E A D A H AW A C A G BP B Y A X A L A X A G A G A G A P A R A P A P A X B X ...

Page 115: ...SHARP CORPORATION Industrial Instruments Group Reliability Quality Contro Department Yamatokoriyama Nara 639 11 Japan 1983 January Printed in Japan s ...

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