Sharp LC-42SV32B, Service Manual

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LC-42SV32B
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in accordance with the I²C bus definition.
The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by
a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW), terminated by an
acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is
read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after
an Ack for Write, and after a NoAck for Read.
Features
■ Two-wire I²C serial interface Supports 400 kHz protocol
■ Single supply voltage:
– 2.5 V to 5.5 V for M24Cxx-W
– 1.8 V to 5.5 V for M24Cxx-R
– 1.7 V to 5.5 V for M24Cxx-F
■ Write Control input
■ Byte and Page Write (up to 16 bytes)
■ Random and Sequential Read modes
■ Self-timed programming cycle
■ Automatic address incrementing
■ Enhanced ESD/latch-up protection
■ More than 1 million write cycles
■ More than 40-year data retention
■ Packages
– ECOPACK® (RoHS compliant)
2.9 U409(M24C32)
General Description
These I
2
C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192x8 bits (M24C64) and 4096x8 bits (M24C32),
and operate down to 2.5 V (for the –W version of each device), and down to 1.8 V (for the -S version of each device).
The M24C64 and M24C32 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages.
Features
Compatible with I2C Extended Addressing
Two Wire I2C Serial Interface Supports 400 kHz Protocol
Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-S
Hardware Write Control
BYTE and PAGE WRITE (up to 32 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention