Sharp LC-26SA1E, Service Manual, Page: 61 / 164

LC-26SA1E/RU, LC-32SA1E/RU
7 – 4
2.1.2 Pin Connections and short description
Pin No. Pin Name Type Description
144 Q0 O 24-bit Output Pixel Data Bus.
143 Q1 O 24-bit Output Pixel Data Bus.
142 Q2 O 24-bit Output Pixel Data Bus.
141 Q3 O 24-bit Output Pixel Data Bus.
140 Q4 O 24-bit Output Pixel Data Bus.
137 Q5 O 24-bit Output Pixel Data Bus.
136 Q6 O 24-bit Output Pixel Data Bus.
133 Q7 O 24-bit Output Pixel Data Bus.
132 Q8 O 24-bit Output Pixel Data Bus.
131 Q9 O 24-bit Output Pixel Data Bus.
130 Q10 O 24-bit Output Pixel Data Bus.
129 Q11 O 24-bit Output Pixel Data Bus.
126 Q12 O 24-bit Output Pixel Data Bus.
125 Q13 O 24-bit Output Pixel Data Bus.
124 Q14 O 24-bit Output Pixel Data Bus.
123 Q15 O 24-bit Output Pixel Data Bus.
119 Q16 O 24-bit Output Pixel Data Bus.
118 Q17 O 24-bit Output Pixel Data Bus.
117 Q18 O 24-bit Output Pixel Data Bus.
116 Q19 O 24-bit Output Pixel Data Bus.
113 Q20 O 24-bit Output Pixel Data Bus.
112 Q21 O 24-bit Output Pixel Data Bus.
111 Q22 O 24-bit Output Pixel Data Bus.
110 Q23 O 24-bit Output Pixel Data Bus.
1 DE O Data enable.
2 HSYNC O Horizontal Sync Output control signal.
3 VSYNC O Vertical Sync Output control signal.
121 ODCK O Output Data Clock.
97 XTALIN I Crystal Clock Input.
96 XTALOUT O Crystal Clock Output.
88 MCLKOUT O Audio Master Clock Output.
87 MCLKIN I Audio Master Clock Input Reference.
86 SCK O I2S Serial Clock Output.
85 WS O I2S Word Select Output.
84 SDO O I2S Serial Data Output.
78 SPDIF O S/PDIF Audio Output.
77 MUTEOUT O Mute Audio Output.
104 INT O Interrupt Output.
102 RESET# I Reset Pin.Active LOW.
32 DSCLO I DDC I2C Clock for Port 0.
31 DSDAO Bi-Di DDC I2C Data for Port 0.
30 DSCL1 I DDC I2C Clock for Port 1.
29 DSDA1 Bi-Di DDC I2C Data for Port 1.
28 CSCL I Configuration I2C Clock.
27 CSDA Bi-Di Configuration I2C Data.
103 SCDT O Indicates active video at HDMI input port.
107 CLK48B Bi-Di Data Bus Latch Enable.
34 R0PWR5V I Port 0 Transmitter Detect.
33 R1PWR5V I Port 1 Transmitter Detect.
101 RSVDL I Reserved, must be tied LOW.
56 RSVD_A Reserved Pin, leave unconnected.
93100 NC – No connect.
9 VREF –
81,82,83 RSVD O
14 AnRPr O Analog Video Red, Pr Output.
17 AnGY O Analog Video Green, Y Output.
20 AnBPb O Analog Video Blue, Pb Output.
11 COMP –
Compensation. Provides compensation for the DAC's internal reference amplifier.
This pin should be connected through capacitors to DACVCC externally.
These capacitors must be close to the pin as possible to avoid any noise pick-up.
10 RSET –
Full Scale Adjust Resistor. A precision(1%)resistor connected between this pin and DACGND controls
the magnitude of the full scale video signal/RESET may need to be ajusted for optimum gain.
This resistor must be as close to the pin as possible to avoid any noise pick-up.