Sharp LC-19LS410UT, Service Manual

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2008-03-14
LC-19LS410UT, LC-22LS510UT
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The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a highspeed CMOS Double Data Rate 2 SDRAM containing 536,870,912 bits. It is internally
configured as a quad-bank DRAM.
The 512Mb chip is organized as either 32Mbit x 4 I/O x 4 bank, 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device.
The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal
and weak strength dataoutput driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of
differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
A 14 bit address bus for x4 and x8 organised components and a 13 bit address bus for x16 components is used to convey row, column, and bank address
devices.
These devices operate with a single 1.8V+/-0.1V power supply and are available in BGA packages.
An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.
1.3. U409 (SII9187ACNU QFN-72)
Introduction
The SiI9187A HDMI Port Processor is the second generation of HDMI devices that support Revision 1.3a of the HDMI Specification. With four HDMI inputs
and a single output, the SiI9187A port processor enhances the functionality of digital TVs using single system on a chip (SoC) solutions with integrated
HDMI 1.3 receivers. The SiI9187A device brings cutting edge innovations like enhanced cable equalization for long cable support, integrated EDID and
CEC functions, and improved ESD protection on all signals connected to the HDMI connector. The port processor is a fully compliant HDMI device that
provides a simple lowcost method of retransmitting digital audio and video to give consumers a truly all-digital experience. Built-in backward compatibility
with DVI 1.0 allows HDMI systems to connect to any DVI 1.0 source.
This device provides additional integrated features, including standby power modes and a built in regulator, which lowers system cost and optimizes board
design and layout.
Features
• Four-input, single-output HDMI port processor
• Improved ESD protection on all signals connected to HDMI connector
• Integrated TMDS receiver and transmitter cores capable of receiving and transmitting at 2.25 Gbps:
• Supports video resolutions up to 1080p, 60 Hz, 12-bit or 720p/1080i, 120 Hz, 12-bit
• Built-in adaptive equalizer provides long cable support even at Deep Color resolutions, enabling the SiI9187A device to work with noisy signals and
many sources, making the sink devices highly interoperable
• Receiver fully complies with DVI 1.0, HDCP 1.3 and HDMI 1.3a specifications
Additional Features
• Built-in Consumer Electronics Control (CEC) support:
• HDMI-compliant CEC I/O simplifies design and lowers the cost for adding CEC support to DTV
• Integrated CEC API lowers overhead requirements on the system microcontroller and design.
• EDID and DDC support for 4 HDMI/DVI ports and 1 VGA port
• 256-byte NVRAM shared between ports loads into SRAM
• 256-byte separate SRAM for each port (5 total)
• Individual control of Hot Plug Detect (HPD) for each port
• 5-volt detect to help speed soft mute of audio while plugging and unplugging
• Controllable by the local I2C bus
• Low-power standby mode to meet Energy Star and other power saving requirements
• Single power 3.3-V source
• Integrated 5 V to 3.3 V Voltage regulator
• 72-pin, 10 mm x 10 mm, 0.5 mm pitch QFN package with enhanced ePad™.
1.4. U602 (AD82581B-LEG LQFP-48 12W)
Features
·
16/18/20/24-bit input with I2S, Left-alignment and Right-alignment data format
· PSNR & DR(A-weighting)
Loudspeaker: 98dB (PSNR), 106dB (DR) @24V
· Multiple sampling frequencies (Fs)