– 41 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC003 92LRCI7272-002: (LC72720NM)
1
VREF
Output
Reference voltage output (VDDA/2).
2
MPXIN
Input
Baseband (multiplexed ) signal input.
3
VDDA
—
Analog system power supply (+5 V).
4
VSSA
—
Analog system ground.
5
FLOUT
Output
Subcarrier output (filter output).
6
CIN
Input
Subcarrier input (comparator input).
7
T1
Input
Test input (This pin must always be connected to ground.).
8
T2
Input
Test input (stand-by control).
0: Normal operation, 1: Stand-by state. (crystal oscillator stopped).
9*
T3 (RDCL)
Input/Output* Test I/O (RDS clock output).
10*
T4 (RDDA)
Input/Output* Test I/O (RDS data output).
11*
T5 (RSFT)
Input/Output* Test I/O (Soft-decision control data output).
12
XOUT
Output
Crystal oscillator output (4.332/8.664 MHz).
13
XIN
Input
Crystal oscillator input. (external reference signal input).
14
VDDD
—
Digital system power supply (+5 V).
15
VSSD
—
Digital system ground.
16*
T6
Input/Output* Test I/O (Error status output, regenerated carrier output, error block count output).
(ERROR/57K/BE1)
17*
T7
Input/Output* Test I/O(Error correction status output, SK detection output, error block count output).
(CORREC/
ARI-ID/BE0)
18*
SYNC
Input/Output* Block synchronization detection output.
19*
RDS-ID
Output
RDS detection output.
20
DO
Output
Data output. Serial data interface (CCB).
21
CL
Input
Clock output. Serial data interface (CCB).
22
DI
Input
Data input. Serial data interface (CCB).
23
CE
Input
Chip enable. Serial data interface (CCB).
24
SYR
Input
Synchronization and RAM address reset (active high).
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications.
VDDA
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
CCB
TEST
VREF
FLOUT
CIN
57 kHz
BPF
(SCF)
SMOOTHING
FILTER
RAM
(24 BLOCK DATA)
ERROR CORRECTION
(SOFT DECISION)
CLK(4.332 MHz)
XIN
XOUT
OSC/DIVIDER
VREF
PLL
(57 kHz)
CLOCK
RECOVERY
(1187.5 Hz)
VDDD
VSSD
RDS-ID
SYNC
SYR
DATA
DECODER
SYNC/CE CONTROLLER
SYNC
DETECT-1
SYNC
DETECT-2
MEMORY
CONTROL
VSSA
MPXIN
DO
CL
DI
CE
T1
T2
T3~T7
+
–
Figure 41 BLOCK DIAGRAM OF IC
