DV-SL8W
SIGNAL
PIN
DESCRIPTION
STATE
48
M_CLOKO
106
O
SDRAM clock output
M_CKE
108
O
SDRAM clock enable
M_A[11]/GPIO
109
I/O
SDRAM address bus [11] or GPIO
M_A[9]
110
O
SDRAM address bus [9]
M_A[8]
111
O
SDRAM address bus [8]
M_A[7]
113
O
SDRAM address bus [7]
M_A[6]
114
O
SDRAM address bus [6]
M_A[5]
115
O
SDRAM address bus [5]
M_A[4]
117
O
SDRAM address bus [4]
M_DQM1
118
O
SDRAM data input/output mask for M_DD[15:8]
M_DQM0
119
O
SDRAM data input/output mask for M_DD[7:0]
M_BA1
121
O
SDRAM bank select address [1]
M_A[10]
122
O
SDRAM address bus [10]
M_A[0]
123
O
SDRAM address bus [0]
M_A[1]
125
O
SDRAM address bus [1]
M_A[2]
126
O
SDRAM address bus [2]
M_A[3]
127
O
SDRAM address bus [3]
M_DD[31]
129
I/O
SDRAM data bus bit 31
M_DD[30]
130
I/O
SDRAM data bus bit 30
M_DD[29]
131
I/O
SDRAM data bus bit 29
M_DD[28]
133
I/O
SDRAM data bus bit 28
M_DD[27]
134
I/O
SDRAM data bus bit 27
M_DD[26]
135
I/O
SDRAM data bus bit 26
M_DD[25]
136
I/O
SDRAM data bus bit 25
M_DD[24]
138
I/O
SDRAM data bus bit 24
M_DQM3/GPIO
139
I/O
SDRAM data input/output mask for M_DD[31:24]
M_DQM2/GPIO
140
I/O
SDRAM data input/output mask for M_DD[23:16]
M_DD[23]
141
I/O
SDRAM data bus bit 23
M_DD[22]
143
I/O
SDRAM data bus bit 22
M_DD[21]
144
I/O
SDRAM data bus bit 21
M_DD[20]
145
I/O
SDRAM data bus bit 20
M_DD[19]
146
I/O
SDRAM data bus bit 19
M_DD[18]
148
I/O
SDRAM data bus bit 18
M_DD[17]
149
I/O
SDRAM data bus bit 17
M_DD[16]
150
I/O
SDRAM data bus bit 16
M_A[12]/GPIO
151
I/O
SDRAM address bus [12] or GPIO
Audio Interface (10)
A_DATA[4] / GPIO
163
I/O
Serial audio data output for channel 9/8 or GPIO
A_IEC_RX/GPIO
164
I/O
IEC-958 receive data
Priority selection
Function
sft_cfg6[4]=1’b1
M_A[11] (default)
(Other)
GPIO[14]
Priority selection
Function
sft_cfg6[6]=1’b1
M_BA1
(Other)
GPIO[15]
Priority selection
Function
sft_cfg6[5]=1’b1
M_A[12] (default)
(Other)
GPIO[18]
Priority selection
Function
sft_cfg3[5]=1’b1
A_DATA[4] (default)
(Other)
GPIO[57]
Priority selection
Function
sft_cfg3[7]=1’b1
A_IEC_RX (default)
(Other)
GPIO[58]
