DV-SL800W
67
IC106 & IC107, COMS DRAM 143MHZ 16MB
Pin Configuration:
Pin Description:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
A11
A10
A0
A1
A2
A3
VDD
50pin TSOP ll
400mil x 825mil
0.8mm pin pitch
Pin
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on the rising
edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one of the
stales among power down, suspend or self refresh.
Chip Select
Command input enable or mask except CLK, CKE and DQM.
Pin Name
Description
CS
Bank Address
Select either one of banks during both RAS and CAS activity.
BA
Address
Row Address: RAD ~ RA10, Coiumn Address: CA0 ~ CA7
Auto-precharge flag: A10
A0 ~ A10
Date Input/Output Mask
DQM control output buffer in read mode and mask input data in write mode.
LDQM, UDQM
Date Input/Output
Multiplexed date input/output pin.
DQ0 ~ DQ15
Power Supply/Ground
Power supply for internal circuit and input buffer
VDD/VSS
Data Output Power/Ground
Power supply for DQ
VDDQ/VSSQ
No Connection
No connection
NC
Row Address Strobe,
Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation.
Refer function fruth table for details.
RAS, CAS, WE
Summary of Contents for DV-SL800W
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