– 55 –
CD-PC1881V
Pin No.
Port Name
Function
1
VDD
Power supply
2-10
DQ0-DQ7
Data input/output
11*,12*
NC
Not used
13
WE
Read/write enable
14
RAS
Row address strobe
15*
NC
Not used
16-19
A0-A3
Address input (row/refresh: A0 to A3) (Column: A0 to A3)
20
VDD
Power supply
21
VSS
Ground
22-26
A4-A8
Address input (row/refresh: A4 to A8) (Column: A4 to A8)
27
OE
Output enable
28,29
UCAS, LCAS
Column address strobe
30*
NC
Not used
31-34
DQ8-DQ11
Data input/output
35
VSS
Ground
36-39
DQ12-DQ15
Data input/output
40
VSS
Ground
ICV3 VHiSDM4260C-1: DRAM (SDM4260C)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Figure 55 BLOCK DIAGRAM OF IC
RAS
LCAS
UCAS
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
VDD
VSS
DQ0
DQ1
DQ7
DQ8
DQ9
DQ15
OE
Lowar
Upper
Clock generating
circuit
Lower data
Input buffer
Lower data
Output buffer
Coidmn decoder
Upper data
Input buffer
A0-A8
A0-A8
I/O control circuit
Memory cell array
Upper data
Output buffer
Roe decoder
Row and column address buffer
14
29
28
13
16
17
18
19
22
23
24
25
26
27
39
32
31
10
3
2
40
35
21
1
20
