Sharp Aquos LC 65D64U, Service Manual

Page: 57 / 152

LC-65D64U
7 – 2
1.10. IC8001 (RH-iXC138WJQZQ)
This LSI is FULL HIGH-DEFINITION 1080P DIGITAL TV SYSTEM-ON-A-CHIP. It combines a cable/terrestrial 4/1024-QAM and 8/16-VSB receiver, a
transport processor, a digital audio processor, a high definition (HD) MPEG video decoder, 2D graphics processing, digital processing of analog video
and audio, analog video digitizer and DAC functions, stereo high-fidelity audio DACs, a 330-MHz millions of instructions per second (MIPS) proces-
sor, and a peripheral control unit providing a variety of television control functions.
The cable/terrestrial receiver directly samples a tuner output with an analog-to-digital converter (ADC). The LSI digitally resamples and demodulates
the signal with recovered clock and carrier timing, filters and equalizes the data, and passes soft decisions to an ATSC A/53 and ITU-T J.83 Annex A/
B/C-compatible decoder. It has an MPEG-2 Digital Video Broadcasting (DVB)-compliant transport processor with advanced section filtering capability,
DVB descrambler, and an MPEG-2 (MP@HL profile) video decoder.
Audio support includes a BTSC and a Dolby AC3/MPEG-2 Layer 1, 2, audio decoder. The LSI provides analog and digital audio/video outputs. A
SPDIF output and a pair of analog outputs (L-R) are provided via the integrated audio DACs. The NTSC analog video decoder is supported by its own
motion adaptive deinterlacing and 3D comb filtering, including 1080i deinterlacing.
The LSI includes advanced 2D graphics processing. Two transport stream inputs are included. The LSI incorporates a complete MIPS32(r)-based
microprocessor subsystem including caches with bridging to memory and a local bus, where external peripherals can be attached. Integrated periph-
erals include two USB 2.0, three UARTs, counter/timers and GPIO controllers.
1.11. IC8452 (RH-iXC268WJQZQ)
The 64-Mbit page mode flash memory device stores the main CPU program.