Sharp AQUOS LC-42XD10E, Service Manual

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LC-42XD10E/RU
5 – 11
4. IC3501/3502: RH-IXB765WJZZ
256Mb DDR SDRAM
Pin No. Pin Name I/O Pin Function
45,46 CK, CK I Clock: CK and CK are differential clock inputs.
All address and control input signals are sampled on the positive edge of CK and negative edge of CK.
Output (read) data is referenced to both edges of CK.
Internal clock signals are derived from CK/CK.
44 CKE I Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
and device input buffers and output drivers.
Taking CKE Low provides PRECHARGE POWER DOWN and SELF REFRESH
operction (all bank idle)
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit, and for output disable.
CKE must be maintained high throughput READ and WRITE accesses.
Input buffers, excluding CK, CK and CKE are disabled during POWER-DOWN.
Input buffers, excluding CKE are disabled during SELF REFRESH.
CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon
1st power up, After VREF has become stable during the power on and initialization
sequence, it must be maintained for proper operation of the CKE receiver.
For proper SELF-REFRESH entry and exit, VREF must be maintained to this input.
24 CS I Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command
decoder.
All commands are masked when CS is registered HIGH.
CS provides for external bank selection on systems with multiple banks.
CS is considered part of the command code.
21-23 RAS, CAS, WE I Command Inputs: RAS, CAS, and WE (along with CS) define the command being
entered.
20,47 LDM,(UDM) I Input Data Mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that input data during a
WRITE access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For the x16, LDM corresponds to the data on DQ0>D7; UDM corresponds to the
data on DQ8>DQ15.
DM may be driven high, low, or floating during READs.
26,27 BA0, BA1 I Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ,WRITE
or PRECHARGE command is being applied.
28-32,
35-42
A [0: 12] I Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one
location out of the memory array in the respective bank.
A10 is sampled during a PRECHARGE command to determine whether the
PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be procreated, the bank is selected by BA0, BA1.
The address inputs also provide the op-code during a MODE REGISTER SET
command.
BA0 and BA1 define which mode register is loaded during the MODE REGISTER
SET command (MRS or EMRS).
2,4,5,7,
8,10,
11,13,
54,56,
57,59,
60,62,
63,65
DQ I/O Data Input/Output: Data bus.
16,51 LDQS,(U)DQS I/O Data Strobe: Output with read data, input with write data.
Edge-aligned with read data, centered in write data.
Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0>D7; UDQS corresponds to
the data on DQ8>DQ15
14,17,
19,25,
43,50,
53,
NC - No Connect: No internal electrical connection is present.
3,9,15,
55,61
VDDQ - DQ Power Supply: +2.5V
±
0.2V. (+2.6V
±
0.1V for DDR400)
6,12,
52,58,
64
VSSQ - DQ Ground.
1,18,33, VDD - Power Supply: +2.5V
±
0.2V. (+2.6V
±
0.1V for DDR400)