Sharp AQUOS LC-42XD10E, Service Manual

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LC-42XD10E/RU
5 – 7
M1 NVM_18 O NVM_[22:16] upper address bits (to-flash memory)
N4 NVM_17 O NVM_[22:16] upper address bits (to-flash memory)
U1 NVM_16 O NVM_[22:16] upper address bits (to-flash memory)
U4 NVM_15 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
T1 NVM_14 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
T2 NVM_13 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
T3 NVM_12 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
T4 NVM_11 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
R1 NVM_10 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
R2 NVM_9 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
R3 NVM_8 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
R4 NVM_7 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
P1 NVM_6 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
P2 NVM_5 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
P3 NVM_4 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
P4 NVM_3 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
N1 NVM_2 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
N2 NVM_1 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
N3 NVM_0 I/O NVMD_[15:0] multiplexed address/data (to-flash memory)
L2 NVMOE_N O Output enable (active low)
M3 NVMWE_N O Write enable (active low)
U2 ENVMALE O Address latch enable.
R7 REXT_LVDS S External Resistor (6.2K
Ω
, 1%)
AC8 PORT_A_29 I Port A data RGB or LVDS (TA1-)
AB8 PORT_A_28 I Port A data RGB or LVDS (TA1+)
AC7 PORT_A_27 I Port A data RGB or LVDS (TB1-)
AB7 PORT_A_26 I Port A data RGB or LVDS (TB1+)
AC6 PORT_A_25 I Port A data RGB or LVDS (TC1-)
AB6 PORT_A_24 I Port A data RGB or LVDS (TC1+)
AC5 PORT_A_23 I Port A data RGB or LVDS (CK1-)
AB5 PORT_A_22 I Port A data RGB or LVDS (CK1+)
AA5 PORT_A_21 I Port A data RGB or LVDS NC
Y5 PORT_A_20 I Port A data RGB or LVDS NC
AC4 PORT_A_19 I Port A data RGB or LVDS (TD1-)
AB4 PORT_A_18 I Port A data RGB or LVDS (TD1+)
AC3 PORT_A_17 I Port A data RGB or LVDS (TE1-)
AB3 PORT_A_16 I Por A data RGB or LVDS (TE1+)
AC1 PORT_A_15 I Port A data RGB or LVDS (TA2-)
AC2 PORT_A_14 I Port A data RGB or LVDS (TA2+)
AB1 PORT_A_13 I Port A data RGB or LVDS (TB2-)
AB2 PORT_A_12 I Port A data RGB or LVDS (TB2+)
AA3 PORT_A_11 I Port A data RGB or LVDS NC
AA4 PORT_A_10 I Port A data RGB or LVDS NC
AA1 PORT_A_9 I Port A data RGB or LVDS (TC2-)
AA2 PORT_A_8 I Port A data RGB or LVDS (TC2+)
Y1 PORT_A_7 I Port A data RGB or LVDS (CK2-)
Y2 PORT_A_6 I Port A data RGB or LVDS (CK2+)
Wl PORT_A_5 I Port A data RGB or LVDS (TD2-)
W2 PORT_A_4 I Port A data RGB or LVDS (TD2+)
V1 PORT_A_3 I Port A data RGB or LVDS (TE2-)
V2 PORT_A_2 I Port A data RGB or LVDS (TE2+)
V3 PORT_A_1 I Port A data RGB or LVDS NC
V4 PORT_A_0 I Port A data RGB or LVDS NC
W4 PORT_ A_PCS1 I/O Port A panel control. NC
W3 PORT_A_PCS2 I Port A panel control. HSYNC_OSC
Y4 PORT_A_PCS3 I Port A panel control. VSYNC_OSC
Y3 PORT_A_PCS4 I/O Port A panel control. NC
AA6 PORT_A_PCS5 I/O Port A panel control. NC
Y7 PORT_A_PCS6 I/O Port A panel control. NC
AA7 PORT_A_REV I/O Port A panel control. NC
Y6 PORT_A_CLK I/O Port A clock.
AB13 PORT_B_16 I/O Port B data. NC
Y13 PORT_B_15 I/O Port B data. NC
AA12 PORT_B_14 I/O Port B data. NC
AC12 PORT_B_13 I/O Port B data. NC