25
MEMORY MAP
(Continued)
21YF30
ADDRESS
DATA
MICON
EEPROM
EEPROM
CHASSIS
CTV FINAL
LAST INITIAL
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
RANGE
WRITE(CPU)
CHECK DATA
CHECK TYPE
CHECK DATA
CHECK TYPE
SETTING DATA
REMARK
2C0
2C1
2C2
2C3
2C4
2C5
2C6
2C7
2C8
2C9
2CA
2CB
2CC
2CD
2CE
2CF
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2DA
2DB
2DC
2DD
2DE
2DF
2E0
2E1
2E2
2E3
2E4
2E5
2E6
2E7
2E8
2E9
2EA
2EB
2EC
2ED
2EE
2EF
2F0
2F1
2F2
2F3
2F4
2F5
2F6
2F7
2F8
2F9
2FA
2FB
2FC
2FD
2FE
2FF
MODEL
MODEL
LETTER NO.
LETTER NO.
*1 0 : individually selectable rating system 1 : threshold selectable rating system
*2 0 : CATEGORY bit mask with (01,05) 1st character 1 : CATEGORY bit mask with (01,05) 2nd character
Summary of Contents for 21YF30
Page 32: ...21YF30 32 SOLID STATE DEVICE BASE DIAGRAM TOP VIEW SIDE VIEW ...
Page 33: ...33 21YF30 M E M O ...
Page 34: ...34 21YF30 WAVEFORMS ...
Page 35: ...35 21YF30 CHASSIS LAYOUT ...
Page 36: ...36 21YF30 1 2 3 4 5 6 7 8 9 10 A B C D E F G H I J BLOCK DIAGRAM PWB A MAIN BLOCK ...
Page 37: ...37 21YF30 10 11 12 13 14 15 16 17 18 19 ...
Page 39: ...39 21YF30 1 2 3 4 5 6 7 8 9 10 A B C D E F G H I J PWB E S CONTROL BLOCK ...
Page 42: ...42 21YF30 1 2 3 4 5 6 7 8 9 10 A B C D E F G H I J SCHEMATIC DIAGRAM MAIN Unit ...
Page 43: ...43 21YF30 10 11 12 13 14 15 16 17 18 19 ...
Page 44: ...44 21YF30 1 2 3 4 5 6 7 8 9 10 A B C D E F G H I J SCHEMATIC DIAGRAM S CONTROL Unit ...
Page 46: ...46 21YF30 1 2 3 4 5 6 7 8 9 10 A B C D E F G H I J PWB A MAIN Unit Component Side ...
Page 47: ...47 21YF30 10 11 12 13 14 15 16 17 18 19 ...
Page 58: ...Ref No Part No Description Code Ref No Part No Description Code 58 21YF30 PACKING OF THE SET ...
Page 59: ...Ref No Part No Description Code Ref No Part No Description Code 59 21YF30 ...