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CHAPTER 9
Introduction
9.1 Introduction
The Cortex-M MPU divides the memory map into a number of regions, and defines the
location, size, access permissions, and memory attributes of each region. The memory
attributes affect the behavior of memory accesses to the region. If the program accesses
a memory location that is prohibited by the MPU, the processor generates a MemManage
fault. Software can also cause other faults like BusFault or UsageFault. embOS-MPU uses
the hardware MPU and automatically setups the MPU region settings. All faults are handled
by embOS-MPU.
Note
The Cortex-M MPU hardware is used by embOS-MPU. You must not enable the Cor-
tex-M MPU in your application. This is automatically handled by embOS.
9.2 Supervisor call
embOS-MPU needs a safe way to switch from an unprivileged task to the privileged OS.
With Cortex-M this is done via the SVC call. A SVC exception handler is necessary to handle
the SVC call. The file
SVCHandler.S
contains the SVC handler. When working with your
own project please ensure that this file is part of your project.
9.3 Fault exceptions
If a task does an invalid operation an exception occurs. With Cortex-M this can either
be a hard fault, a memory manage fault, a bus fault or a usage fault. These faults are
handled in
HardFaultHandler.S
,
MemManageHandler.S
,
BusFaultHandler.S
and
Usage-
FaultHandler.S
. When working with your own project please ensure that these files are
part of your project and the fault handlers are inserted in your vector table. embOS-MPU
Cortex-M enables these faults.
9.4 Alignment
The Cortex-M MPU requires memory alignment. Please ensure the used memory regions
are aligned accordingly: The size must be a power of two, at least 32 bytes and the base
address must be divisible by the size with zero remainder. embOS-MPU checks the align-
ment and calls
OS_Error()
in case of a wrong alignment. embOS setups MPU regions for
newly created tasks. One MPU region is setup for the task stack.
Example:
//
// Stack for unprivileged task. This will be used for MPU
// settings and with Cortex-M it requires alignment.
// In most cases, the same power of 2 will work for both size and alignment
//
#pragma
data_alignment=
512
OS_STACKPTR
int
StackLP[
128
];
embOS-MPU for Cortex-M and IAR
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