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Q7-928

 

Q7-928 User Manual - Rev. First Edition: 1.0 - Last Edition: 3.0 - Author: S.B. - Reviewed by P.Z Copyright © 2016 SECO S.r.l.  

32 

3.2.3.6

 

SDI/O interface signals 

As previously told in paragraph 3.2.2, NXP i.MX6 processors offer many different SDIO interfaces, that can be used independently one from the other to implement 
different mass storages (internal eMMC, internal SD Card, external SDI/O interface). 

Each of the uSDHC controllers complies with: 

 

SD Host Controller Standard Specification version 3.0 

 

MMC System Specification version 4.2/4.3/4.4/4.41 

 

SD Memory Card Specification version 3.0 and supports the Extended Capacity SD Memory Card 

 

SDIO Card Specification version 3.0 

SDI/O port #1 is externally accessible through golden edge finger connector, and can work in 1-bit, 4-bit and 8-bit modes (8-bit mode for MMC support). 

Signals involved with SDI/O interface are the following: 

SDIO_CD#:  Card  Detect  Input.  Active  Low  Signal,  electrical  level  +3.3V_S  with  10k

Ω

  pull-up  resistor.  This  signal  must  be  externally  pulled  low  to  signal that  a 

SDIO/MMC Card is present. 

SDIO_CLK: Clock Line (output), 52MHz maximum frequency for MMC High Speed Mode, 50 MHz maximum frequency for SD/SDIO High Speed Mode 

SDIO_CMD: Command/Response line. Bidirectional signal, electrical level +3.3V_S, used to send command from Host (i.MX6 processor) to the connected card, 
and to send the response from the card to the Host. 

SDIO_LED: LED output signal, electrical level +3.3V_S. It is used to drive an external LED when there are transfers on SD Bus. 

SDIO_WP: Write Protect bidirectional signal, electrical level +3.3V_S. It is used to communicate the status of Write Protect switch on external SD/MMC card. 

SDIO_PWR#: SD power enable, tied to GND through a 47k

Ω

 pull-down resistor. 

SDIO_DAT[0÷7]:  SDIO  data  bus.  SDIO_DAT0  signal  is  used  for  all  communication  modes.  SDIO_DAT[1÷3]  signals  are  required  for  4-bit  SD/SDIO/MMC 
communication modes. SDIO_DAT[4÷7] are used only for 8-bit MMC communication mode. 

3.2.3.7

 

Audio interface signals 

Q7-928 module supports AC

97 audio format, thanks to native support offered by the processor to this audio codec standard. 

Both AC

97 Fixed and variable mode are supported, min frame rate 8kHz, max Frame rate 48kHz 

Here following the signals related to Audio AC

97 interface: 

HDA_SYNC: AC

97 Serial Bus Synchronization. Output from the module to the Carrier board, electrical level +3.3V_S. 

HDA_RST#: AC

97 Codec Reset. Active Low signal Output from the module to the Carrier board, electrical level +3.3V_S. 

Summary of Contents for Q7-928

Page 1: ...Q7 928 Qseven Rel 2 0 Compliant Module with NXP i MX6 Processor...

Page 2: ...eatures revised Block Diagram updated Power consumption added Qseven golden finger pinout updated SB 2 0 30th September 2013 New manual release SB 2 1 22nd November 2013 Minor corrections Technical fe...

Page 3: ...1 8 Reference specifications 10 OVERVIEW 12 Chapter 2 2 1 Introduction 13 2 2 Technical Specifications 14 2 3 Electrical Specifications 15 2 3 1 Power Consumption 15 2 3 2 Power Rails meanings 16 2 3...

Page 4: ...1 0 Last Edition 3 0 Author S B Reviewed by P Z Copyright 2016 SECO S r l 4 Chapter 1 Warranty Information and assistance RMA number request Safety Electrostatic Discharges RoHS compliance Terminolog...

Page 5: ...A authorisation number must be put both on the packaging and on the documents shipped with the items which must include all the accessories in their original packaging with no signs of damage to or ta...

Page 6: ...nter it is possible to send the faulty product to the SECO Repair Centre In this case follow this procedure o Returned items must be accompanied by a RMA Number Items sent without the RMA number will...

Page 7: ...high voltages caused by static electricity could damage some or all the devices and or components on board 1 6 RoHS compliance The Q7 928 module is designed using RoHS compliant components and is man...

Page 8: ...nsfer data both on the rising and on the falling edge of the clock DDR3 DDR 3rd generation DVI Digital Visual interface a type of display video interface FFC FPC Flexible Flat Cable Flat Panel Cable F...

Page 9: ...implementing the Physical Layer of ISO OSI 7 model for communication systems PWM Pulse Width Modulation PWR Power RGMII Reduced Gigabit Media Independent Interface a particular interface defining the...

Page 10: ...om content dam www public us en documents product specifications high definition audio specification pdf HDMI http www hdmi org index aspx I2C http www nxp com documents other UM10204_v5 pdf JTAG http...

Page 11: ...ome SDIO https www sdcard org developers overview sdio SM Bus http www smbus org specs TMDS http www siliconimage com technologies tmds USB http www usb org developers docs usb_20_070113 zip NXP i MX6...

Page 12: ...r Manual Rev First Edition 1 0 Last Edition 3 0 Author S B Reviewed by P Z Copyright 2016 SECO S r l 12 Chapter 2 Introduction Technical Specifications Electrical Specifications Mechanical Specificati...

Page 13: ...he first one is a 24 bit Single Dual Channel LVDS interface which can be configured to work as two independent 24 bit Single Channel interfaces The other display interface is i MX6 s native HDMI port...

Page 14: ...ufacturers 1GB 10 9 Byte Some OS like for example Windows intends 1GB 1024 3 byte so global capacity shown for Disk Properties will be less than expected Please also consider that a portion of disk ca...

Page 15: ...needs a carrier board for its normal working All connections with the external world come through this carrier board which provide also the required voltage to the board deriving it from its power sup...

Page 16: ...xamples 5V_A 3 3V_A Other suffixes are used for application specific power rails which are usually derived from same value of voltage switched rails for example 3 3V_CAM is derived from 3 3V_S and so...

Page 17: ...the total current absorbed by the Q7 928 module in the boot phase from POWER ON moment until the completion of the boot The data shown in figure 3 are related to the module Q7 928 with iMX6 Quad Core...

Page 18: ...us connector heights for different carrier board applications needs Qseven specification suggests two connector heights 7 8mm and 7 5mm but it is also possible to use different connector heights also...

Page 19: ...MFG LPC or GPIO PWM Timer IN Lattice MachXO LCMXO640 CPLD SMSC USB2514 USB2 0 Hi Speed Hub Controller Texas Instruments MSP430F2232 microcontroller Embedded MMC Disk SD Slot Camera Interface NXP i MX...

Page 20: ...Q7 928 Q7 928 User Manual Rev First Edition 1 0 Last Edition 3 0 Author S B Reviewed by P Z Copyright 2016 SECO S r l 20 Chapter 3 Introduction Connectors description...

Page 21: ...are available through a single card edge connector In addition a camera FFC FPC connector card slot is present on the side of the board to take advantage of the integrated ISP Image Signal Processing...

Page 22: ...is limited to 2 lanes only Here following is shown the meaning of various pins of the connector Pins 1 17 8 bit parallel format arranged to guarantee 8 bit alignment LSB for ITU BT 656 format voltage...

Page 23: ...7 928 CPU module Therefore please refer to the following table for a list of effective signals reported on MXM connector For accurate signals description please consult the following paragraphs NOTE E...

Page 24: ...O SDIO SDIO I O SDIO_CD 43 44 SDIO_LED O SDIO SDIO O SDIO_CMD 45 46 SDIO_WP I O SDIO SDIO O SDIO_PWR 47 48 SDIO_DAT1 I O SDIO SDIO I O SDIO_DAT0 49 50 SDIO_DAT3 I O SDIO SDIO I O SDIO_DAT2 51 52 SDIO...

Page 25: ...A1 103 104 LVDS_B1 O LVDS LVDS O LVDS_A1 105 106 LVDS_B1 O LVDS LVDS O LVDS_A2 107 108 LVDS_B2 O LVDS LVDS O LVDS_A2 109 110 LVDS_B2 O LVDS LVDS O LVDS_PPEN 111 112 LVDS_BLEN O LVDS LVDS O LVDS_A3 113...

Page 26: ...63 164 N C N A PWR GND 165 166 GND PWR N A N C 167 168 N C N A N A N C 169 170 N C N A UART O UART0_TX 171 172 N C N A N A N C 173 174 N C N A N A N C 175 176 N C N A UART I UART0_RX 177 178 N C N A P...

Page 27: ...ng the signals involved in PCI express management PCIE0_TX PCIE0_TX PCI Express lane 0 Transmitting Output Differential pair PCIE0_RX PCIE0_RX PCI Express lane 0 Receiving Input Differential pair PCIE...

Page 28: ...C1 2 C1 4 C2 5 C2 6 V 3 V 7 T1IN 11 EN 1 R1OUT 9 N C 12 T1OUT 13 SHDN 16 R1IN 8 N C 10 VCC 15 GND 14 C1 CC 100nF 25V C2 CC 100nF 25V UART0_RX UART0_TX C5 CC 100nF 25V C4 CC 100nF 25V C3 CC 100nF 25V 3...

Page 29: ...w Output signal electrical level 3 3V_S GBE_LINK Ethernet controller link indicator Active Low Output signal Electrically tied to GBE_ACT signal GBE_LINK100 Ethernet controller 100Mbps link indicator...

Page 30: ..._ID USB ID Input electrical level 3 3V_S 10k pull up This signal must be driven as an open collector signal by external circuitry placed on the carrier board It must be tied to GND when USB Port 1 has...

Page 31: ...set USB Port 1 in Client mode Q4 2N7002 R9 R 100K R5 R 100K 3 3V_A 3 3V_A C1 CC 100nF SUS_S5 3 3V_A C16 CC 100nF Q2 2N7002 Q3 2N7002 J1 JUMPER 1 2 U3 NC7S08 1 2 4 5 3 3 3V_A C18 CT 47uF 10V C13 CC 10...

Page 32: ...maximum frequency for SD SDIO High Speed Mode SDIO_CMD Command Response line Bidirectional signal electrical level 3 3V_S used to send command from Host i MX6 processor to the connected card and to s...

Page 33: ...sible to configure LVDS output so that it can be used as One single channel 18 or 24 bit output max resolution supported 1366 x 768 60fps One dual channel 18 or 24 bit output max resolution supported...

Page 34: ...module which provides a HDMI standard interface for HDMI1 4a compliant displays By using HDMI interface along with two LVDS single channel interfaces it is possible to drive up to 3 independent displ...

Page 35: ...HDMI_CTRL_CLK HDMI_CTRL DAT U1 SN74LVC1G14DBVR 2 3 4 5 L1 BLM18PG121SN1 D1 D1 GND GND CK D2 GND D2 D0 D0 CK SDA RSVD SCL GND CEC GND TYPE A GND 5V HPD CN1 WHDM 19D5L1BF3U4W 1 2 3 4 5 6 7 8 9 10 11 12...

Page 36: ...on Qseven golden finger connector are General Purpose I Os bidirectional signals at 3 3V_S electrical level Programming of these GPIOs can be made using dedicated APIs supplied by SECO or through Linu...

Page 37: ...in case that the system is placed to one of the two extremities of CAN Line If this termination is required simply plug a jumper in position J1 3 2 3 13 Power Management signals According to Qseven s...

Page 38: ...unconnected if not used on the carrier board LID_BTN LID button Input active low 3 3V_A electrical level signal with 10k pull up resistor This signal can be driven using a LID Switch on the carrier b...

Page 39: ...l electrical level 3 3V_S with a 4k7 pull up resistor It is managed by i MX6 processor s I2C1 controller GP0_I2C_CLK general purpose I2C Bus clock line Bidirectional signal electrical level 3 3V_S wit...

Page 40: ...vel Pin 208 MFG_NC2 signal Pin 209 MFG_NC1 signal LOW UART_DEBUG_RX UART_DEBUG_TX HIGH JTAG_TDI JTAG_TDO In case MFG_NC4 signal is not driven externally then an internal pull down makes available UART...

Page 41: ...Q7 928 Q7 928 User Manual Rev First Edition 1 0 Last Edition 3 0 Author S B Reviewed by P Z Copyright 2016 SECO S r l 41 Chapter 4 Thermal Design...

Page 42: ...ecessary to consider carefully the heat generated by the module in the assembled final system and the scenario of utilisation Until the module is used on a development Carrier board on free air just f...

Page 43: ...Q7 928 Q7 928 User Manual Rev First Edition 1 0 Last Edition 3 0 Author S B Reviewed by P Z Copyright 2016 SECO S r l 43 Standard Heatspreader dimensions...

Page 44: ...Q7 928 Q7 928 User Manual Rev First Edition 1 0 Last Edition 3 0 Author S B Reviewed by P Z Copyright 2016 SECO S r l 44 Standard Heatsink dimensions...

Page 45: ...7 928 User Manual Rev First Edition 1 0 Last Edition 3 0 Author S B Reviewed by P Z Copyright 2016 SECO S r l 45 SECO Srl Via Calamandrei 91 52100 Arezzo ITALY Ph 39 0575 26979 Fax 39 0575 350210 www...

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