Seagate Medalist ST31082A, Product Manual

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Host Interface Chapter 5
Technical Reference Manual Page 29
Host Demand Mode DMA 16-bit Interface Timing Values
The values* in the table below refer to the timing diagram in figure 5-4.
Symbol
Parameter: Min: Max: Units:
T1
+DMARQ low from -IOR/-IOW low 60 ns
T2
-DACK hold from -IOR/-IOW high 10 ns
T3
-DACK low to -IOR/-IOW low 10 ns
T4
-IOR/-IOW pulse width 60 ns
T5
--IOR/-IOW cycle time 120 ns
T6
-IOR low to HDB[15:0] active 30 ns
T7
-IOR high to HDB[15:0] inactive 5 ns
T9
HDB[15:0] set-up to -IOW high 20 ns
T10
HDB[15:0] hold from -IOW high 10 ns
* Under conditions equivalent to a 330 ohm pull-up and a 56pf load. Cable type and length
may affect the values measured at the drive or host interface
Figure 5-4
Interface DMA Timing Diagram
-DACK
HDB[15:0]
(Read)
HDB[15:0]
(Write)
+DMARQ
-IOR/-IOW
T1
T2
T10
T3
T5
T7
T6
T9
541_5_4
T4