Seagate BarraCuda 510 SSD, Product Manual

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Seagate BarraCuda 510 SSD Product Manual, Rev A 14
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31 PETp1
PCIe TX Differential signal defined by the PCI Express M.2 spec
32 N/C
No connect
33 GND
Ground
34 N/C
No connect
35 PERn1
PCIe RX Differential signal defined by the PCI Express M.2 spec
36 N/C
No connect
37 PERp1
PCIe RX Differential signal defined by the PCI Express M.2 spec
38 N/C
No connect
39 GND
Ground
40 SMB_CLK (I/O)(0/1.8V)
SMBus Clock; Open Drain with pull-up on platform
41 PETn0
PCIe TX Differential signal defined by the PCI Express M.2 spec
42 SMB_DATA (I/O)(0/1.8V)
SMBus Data; Open Drain with pull-up on platform.
43 PETp0
PCIe TX Differential signal defined by the PCI Express M.2 spec
44 ALERT#(O) (0/1.8V)
Alert notification to master; Open Drain with pull-up on platform;
Active low.
45 GND
Ground
46 N/C
No connect
47 PERn0
PCIe RX Differential signal defined by the PCI Express M.2 spec
48 N/C
No connect
49 PERp0
PCIe RX Differential signal defined by the PCI Express M.2 spec
50 PERST#(I)(0/3.3V)
PE-Reset is a functional reset to the card as defined by the PCIe Mini
CEM specification.
51 GND
Ground
52 CLKREQ#(I/O)(0/3.3V)
Clock Request is a reference clock request signal as defined by the
PCIe Mini CEM specification; Also used by L1 PM Sub-states.
53 REFCLKn
PCIe Reference Clock signals (100 MHz)
defined by the PCI Express M.2 spec.
54 PEWAKE#(I/O)(0/3.3V)
PCIe PME Wake.
Open Drain with pull up on platform; Active Low.
55 REFCLKp
PCIe Reference Clock signals (100 MHz)
defined by the PCI Express M.2 spec.
56 Reserved for MFG DATA
Manufacturing Data line. Used for SSD manufacturing only.
Not used in normal operation.
Pins should be left N/C in platform Socket.
Table 7 Pin Descriptions (continued)
Pin No. PCIe Pin Description