5
Switch Interrupt Pin
Interrupt
1 PC_IRQ3
6 PC_IRQ9
2 PC_IRQ4
7 PC_IRQ10
3 PC_IRQ5
8 PC_IRQ11
4 PC_IRQ6
9 PC_IRQ12
5 PC_IRQ7
10 PC_IRQ15
Figure 4 Switch Positions for PC Interrupts
Flex/104A Reset Switch
Reset SW1 provides a means for resetting the Flex/104A. Pressing this button will cause
the on board the FPGA to reload. It will not reset the IndustryPacks.
PC/104 Accesses
The Flex/104A requires wait states to be inserted in any PC/104 bus cycle that accesses
the IP bus. The necessary wait states are inserted automatically by the logic on board
the Flex/104A using the IOCHRDY* signal. The BIOS of some older computers,
however, will allow the user to select the number of wait states the PC/104 bus expects.
If the BIOS is set up for zero wait state accesses, the Flex/104A will not operate correctly
since the IOCHRDY* signal is ignored. Selecting one or more of wait states will correct
the problem
IP Addressing on the Flex/104A
Currently, only 16-bit accesses to IndustryPacks on board the Flex/104A are permitted.
In addition, the Flex/104A does not recognize nor reserve a location for the IP A0
(address bit zero) bit. This means that all IP address values listed in User Manuals, other
than those designed by Wavetron Microsystems, must be shifted to the right by one bit
before it is used on the Flex/104A. As an example, consider an IP, which according to
the register map in its user manual, has a control register that is located at an offset of
0x40 on I/O Space. Because the Flex/104A does not recognize the A0 bit in the address,
the adjusted offset for the register is 0x20.
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