SBS Technologies 466-1, Hardware Manual

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Model 466-1 Adapter
CSR Accessed From The SBus 47
CLEAR ERRORS (bit 7): When set, a one-shot signal is generated to clear
error latches. Bit 7 always reads as "0".
BYTE SWAP ON BYTE OPERATION (bit 6): Writing a "1" to bit 6 swaps
during a byte data transfer the byte lanes that data are transferred on. Both
SBus and VMEbus use the big-endian byte ordering; consequently, this bit
should be cleared for typical SBus to VMEbus activity.
WORD SWAP ON LONGWORD OPERATIONS (bit 5): When set and a
longword is transferred with bus sizing, address bit
A1 is inverted. Bit 5 is
not used in the Model 466-1 application because the VMEbus adapter card is
a 32-bit card.
ERROR INTERRUPT ENABLE (bit 2): Must be set to "1" to enable the
adapter to generate error interrupts. The
Interrupt Enable bit (bit 0) must
also be set. For error polling, bit 2 should be cleared.
INTERRUPT ENABLE (bit 0): Must be set to "1" to enable the SBus adapter
card to activate a SBus interrupt signal. This bit is cleared at system reset.
6.1.2 Local Status Register
The Local Status Register (I/O address = 020 0002 hex ) is a read-only register
located on the SBus adapter card. This register reflects the status of several
error sources and can be read during normal operation to determine if errors
are pending.
If an error sets a bit in the Local Status Register, the Clear Errors bit in
the Local Command Register can be set to reset the error latches.
All status bits are active high when enabled.