– 3 –
Table 1-1. CCD Pin Description
Fig. 1-1. CCD Block Diagram
1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CA1 CIRCUIT DESCRIPTION
1. IC Configuration
IC901 (ICX488EQF) CCD imager
IC905 (H driver, CDS, AGC and A/D converter)
2. IC901 (CCD imager)
[Structure]
Interline type CCD image sensor
Image size
Diagonal 6.67 mm (1/2.7 type)
Pixels in total
2396 (H) x 1766 (V)
Recording pixels
2288 (H) x 1712 (V)
Pin No.
1
Symbol
2
3
4
5
6
7
8
9
10
Vø
6
Vø
5B
Vø
5A
Vø
4
Vø
3B
Vø
3A
Vø
2
Vø
ST
Vø
HLD
Pin Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Horizontal addition control clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Horizontal addition control clock
Vø
1
Vertical register transfer clock
Pin No.
13
Symbol
14
15
16
17
18
19
20
21
22
V
OUT
V
DD
øRG
Hø
1B
Hø
2B
GND
øSUB
Hø
1A
Hø
2A
Pin Description
Signal output
Circuit power
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Horizontal register transfer clock
GND
Substrate clock
Horizontal register transfer clock
C
SUB
Substrate bias
3. IC902, IC903 (V Driver) and IC905 (H driver)
An H driver and V driver are necessary in order to generate
the clocks (vertical transfer clock, horizontal transfer clock
and electronic shutter clock) which driver the CCD.
IC902 and IC903 are V driver. In addition the XV1-XV6 sig-
nals which are output from IC101 are the vertical transfer
clocks, and the XSG signal is superimposed at IC902 and
IC903 in order to generate a ternary pulse. In addition, the
XSUB signal which is output from IC101 is used as the sweep
pulse for the electronic shutter. A H driver is inside IC905,
and H1, H2 and RG clock are generated at IC905.
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to Pin
(27) of IC905. There are inside the sampling hold block, AGC
block and A/D converter block.
The setting of sampling phase and AGC amplifier is carried
out by serial data at Pin (32). The video signal is carried out
A/D converter, and is output by 12-bit.
Fig. 1-2. IC905 Block Diagram
11
GND
GND
12
GND
GND
Protection transistor bias
23
GND
GND
24
V
L
8
1
24
2
3
4
5
6
7
21
22
23
9
17
19
18
V
L
V
DD
10
20
11
12
16
15
GND
Ø
SUB
C
SUB
H
Ø
1A
H
Ø
2A
V
Ø
1
V
Ø
2
V
Ø
3A
V
Ø
3B
V
Ø
4
V
Ø
5A
V
Ø
5B
V
Ø
6
V
Ø
ST
V
Ø
HLD
14
13
V
OUT
GND
GND
Ø
RG
H
Ø
2B
H
Ø
1B
Gb
B
R
Gb
R
Gb
Gr
B
Gr
B
B
Gr
B
Gr
R
Gb
R
Gb
Gb
B
R
Gr
R
Gr
Gb
R
B
Gr
Gb
R
B
Gr
B
Gr
R
Gb
Gr
B
R
Gb
GND
(Note)
(Note) : Photo sensor
Horizontal register
Vertical register
CCDIN
RG
H1-H4
VD
HD
SDATA
SCK
SL
CLI
DOUT
VRB
VRT
PRECISION
TIMING
CORE
SYNC
GENERATOR
PxGA
VGA
ADC
12
2~36 dB
VREF
CLAMP
INTERNAL
REGISTERS
INTERNAL
CLOCKS
CDS
CLAMP
HORIZONTAL
DRIVERS
4
