– 4 –
Fig. 1-3. IC901 Block Diagram
3. IC901 (V Driver)
A V driver (IC901) is necessary in order to generate the clocks
(vertical transfer clock and electronic shutter clock) which
driver the CCD.
Setting to internal generator (PREREG and POSTREG) by
the serial signal (SCLK, SAV (0:2) and SDV (0:5)) which are
output from IC101, and output to the vertical transfer clock.
The serial signal (SCLK, SAV (0:2) and SDV (0:5)) which are
output from IC101 are superimposed at internal driver (VER-
TICAL DRIVER) to output to the CCD.
XV [MS]
12 bits
DECODER
XV [MS]
12 bits
PREREG
POSTREG
VERTICAL
DRIVERS
XV [LS]
12 bits
XV [LS]
12 bits
XSG [MS]
12 bits
XSG [MS]
12 bits
XSG [LS]
12 bits
XSG [LS]
12 bits
DRVMISC
12 bits
DRVMISC
12 bits
Fig. 1-4. IC905 Block Diagram
4. IC905 (H Driver, CDS, AGC and A/D converter)
IC905 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver and reset pulse for CCD
image sensor are generated inside H1, H2, H3, H4, HL and
RG output to CCD.
The video signal which is output from the CCD is input to pin
(25) of IC905. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the VGA (VGA: Variable Gain Amplifier). It is con-
verted internally into a small-amplitude actuating signal
(LVDS), and is then input to IC101. The gain of the VGA am-
plifier is controlled by pins (32), (33) and (34) using serial
signals which is output from IC101.
CCDINP
HL
H1 TO H4
HD
SDATA
SCK
SL
REFB
REFT
PRECISION
TIMING
GENERATOR
TG CORE
VGA
12-BIT
ADC
6~42 dB
VREF
CLAMP
INTERNAL
REGISTERS
INTERNAL
CLOCKS
CDS
HORIZONTAL
DRIVERS
4
ADDI7000
-3, 0, +3, +6dB
VD
CLI
RG
GP01
3V INPUT
1.8V OUTPUT
LDO
REG
GP02
TCLKP
REDUCED
RANGE
LVDS
OUTPUT
TCLKN
DOUT0P
DOUT0N
DOUT1P
DOUT1N
CCDINM
