– 3 –
Fig. 1-1.Optical Black Location (Top View)
Pin No.
Symbol
Pin Description
Waveform
Voltage
Table 1-1. CCD Pin Description
When sensor read-out
Fig. 1-2. CCD Block Diagram
1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CCD CIRCUIT DESCRIPTION
1. IC Configuration
The CCD peripheral circuit block basically consists of the fol-
lowing ICs.
IC903 (MN39630PMJ-A)
CCD imager
IC901 (AN20113A)
V driver
IC905 (AD9971BCPZRL)
CDS, AGC, A/D converter,
H driver, vertical TG
2. IC903 (CCD)
[Structure]
1/2.5 inch positive pixel-type color frame-reading fixed pic-
ture elements
7.21 million pixels
Optical size
1/2.5 type format
Effective pixels
3096 (H) X 2328 (V)
Pixels in total
3152 (H) X 2342 (V)
Optical black
Horizontal (H) direction: Front 12 pixels, Rear 44 pixels
Vertical (V) direction:
Front 6 pixels, Rear 8 pixels
Dummy bit number
Horizontal : 28 Vertical :7
1, 4, 5, 8
9, 12
10, 11, 13, 14
18, 19
V
1A,
V
1B,
V
3A,
V
3B
V
2,
V
4
Vertical shift register clock pulse
Vertical shift register clock pulse
GND
-6.0 V, 0 V, 12 V
0 V
Vertical shift register clock pulse
GND
V
5R,
V
6,
V
7R,
V
8
-6.0 V, 0 V
-6.0 V, 0 V
V
OUT
Power
CCD output
Substrate clock
DC
Aprox. 8 V
(Different from every CCD)
DC
Aprox. 10 V
12 V
VDD1, VDD2
26
15, 17
16
ØVSUB
GND
Protection P well
ØHL
Horizontal shift register clock pulse
Horizontal shift register clock pulse
ØH
1A,
ØH
2A,
ØH
1B,
ØH
2B
0 V, 3.0 V
22, 23, 27, 28
21
2, 3, 6, 7
V
5A,
V
5B,
V
7A,
V
7B
Vertical shift register clock pulse
Substrate control
SUB SW
25
0, 3.3 V (When importing all
picture element: 3.5 V)
-6.0 V, 0 V, 12 V
ØRG
Reset pulse
20
PT
24
DC
12.5 V, 16 V
-6 V
0 V, 3.0 V
DC
8
7
ø
V5A
1
2
3
4
5
6
ø
V5B
ø
V6
ø
V7R
ø
V7A
ø
V7B
ø
V8
9
ø
V4
10
ø
V3B
11
ø
V3A
ø
V5R
12
ø
V2
13
ø
V1B
14
ø
V1A
21 22
ø
H1A
28
27
26
25
24
23
ø
H2A
PT
SUBSW
SUB
ø
H1B
ø
H2B
20
ø
RG
19
GND2
18
GND1
ø
HL
17
VDD2
16
VO
15
VDD1
Photo diode
Output part
Vertical shift register
Horizontal shift register
Pin 1
8
6
44
12
H
V
Pin 15
