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1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CCD CIRCUIT DESCRIPTION
1. IC Configuration
The CCD peripheral circuit block basically consists of the fol-
lowing ICs.
IC914 (ICX665SQC) CCD imager
IC905 (ADDI7000BCPZRL) CDS, AGC, A/D converter,
H driver
IC901 (LR366877) V driver
2. IC914 (CCD)
Interline type CCD image sensor
Optical size
1/2.3 type
Effective pixels
3264 (H) x 2448 (V)
Pixels in total
3336 (H) x 2484 (V)
Optical black
Horizontal (H) direction: Front 6 pixels, Rear 39 pixels
Vertical (V) direction: Front 12 pixels, Rear 2 pixels
Dummy bit number Horizontal : 14
Fig. 1-1.Optical Black Location (Top View)
Fig. 1-2. CCD Block Diagram
Table 1-1. CCD Pin Description
Pin No.
1
Symbol
2
3
4
5
6
7
8
9
10
øSUB
V
L
øVOG
øLV
VGND
Vø
1A
Vø
1B
Vø
3A
Vø
3B
Pin Description
Substrate clock
Protection transistor bias
Vertical register end stage control clock
Vertical register transfer clock
Vertical - holizontal shift clock
Pixel area GND
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vø
2
Vertical register transfer clock
Pin No.
15
Symbol
16
17
20
21
22
23
24
25
26
Vø
5C
Vø
6S1
Vø
6S2
V
OUT
V
DD
NC
øRG
AGND
AGND
Pin Description
Vertical register transfer clock
Vertical register transfer clock
Vertical storage control clock 2
Circuit GND
Signal output
Circuit power
NC
Reset gate clock
Circuit GND
NC
NC
11
Vø
3C
Vertical register transfer clock
12
Vø
4
Vertical register transfer clock
13
Vø
5A
Vertical register transfer clock
14
Vø
5B
Vertical register transfer clock
27
HGND
Horizontal transfer register GND
28
CSUB
Substrate bias
29
SUB_CONT
Substrate bias control
30
NC
NC
31
NC
NC
32
NC
NC
33
øLH1
Horizontal register end stage transfer clock
34
øH1
Horizontal register transfer clock
35
øH2
Horizontal register transfer clock
36
øH3
Horizontal register transfer clock
2
12
39
6
H
V
Pin 1
Pin 20
18
Vø
ST2
Vertical storage control clock 2
19
Vø
ST1
Vertical storage control clock 1
37
Vø
HLD1
Vertical signal hold clock 1
38
Vø
HLD2
Vertical signal hold clock 2
