-54-
72
PD16/D16/IRQ0
PW_PG_SEL
PW365 232C Write SW(SH="H",PIXEL="L")
I
73
PD15/D15
DATA15
Data Bus 15
I/O
74
PD14/D14
DATA14
Data Bus 14
I/O
75
PD13/D13
DATA13
Data Bus 13
I/O
76
PD12/D12
DATA12
Data Bus 12
I/O
77
VCC
5V
78
PD11/D11
DATA11
Data Bus 11
I/O
79
VSS
GND
80
PD10/D10
DATA10
Data Bus 10
I/O
81
PD9/D9
DATA9
Data Bus 9
I/O
82
PD8/D8
DATA8
Data Bus 8
I/O
83
PD7/D7
DATA7
Data Bus 7
I/O
84
PD6/D6
DATA6
Data Bus 6
I/O
85
VCC
5V
86
PD5/D5
DATA5
Data Bus 5
I/O
87
VSS
GND
88
PD4/D4
DATA4
Data Bus 4
I/O
89
PD3/D3
DATA3
Data Bus 3
I/O
90
PD2/D2
DATA2
Data Bus 2
I/O
91
PD1/D1
DATA1
Data Bus 1
I/O
92
PD0/D0
DATA0
Data Bus 0
I/O
93
VSS
GND
94
XTAL
XTAL
OSC Signal Input
I
95
MD3
Mode-3
Mode-3 I
96
EXTAL
EXTAL
OSC Signal Output
O
97
MD2
Mode-2
Mode-2
I
98
NMI
NONMASK
NONMASK
I
99
VCC (FWP)
FWP
Flash Memory Write Mode
I
100
PA16/AH
FLASH MODE
FWP Control
O
101
PA17/WAIT
O
102
MD1
Mode-1
Mode-1
I
103
MD0
Mode-0
Mode-0
I
104
PLLVCC
PLLVCC
PLL Vcc
105
PLLCAP
PLLCAP
PLL Filter
106
PLLVSS
PLLGND
PLL Gnd
107
PA15/CK
M-CLK
CPU Clock Output (Auto Image FPGA)
O
108
RES
Reset
Reset Active
L
I
109
PE0/TIOC0A/DREQ0
PCTL
CXD3511Q
O
110
PE1/TIOC0B/DRAK0
SCL 6
IIC Bus 6 Clock
I/O
111
PE2/TIOC0C/DREQ1
SDA 6
IIC Bus 6 Data
I/O
112
VCC
5V
113
PE3/TIOC0D/DRAK1
SDA 3
IIC Bus 3 Data
I/O
114
PE4/TIOC1A
SCL 3
IIC Bus 3 Clock
I/O
115
PE5/TIOC1B
SDA 4
IIC Bus 4 Data
I/O
116
PE6/TIOC2A
SCL 4
IIC Bus 4 Clock
I/O
117
VSS
GND
118
PF0/AN0
KEY1
Top Control Keys-1 (A/D Input)
I
119
PF1/AN1
KEY2
Top Control Keys-2 (A/D Input)
I
120
PF2/AN2
KEY3
Top Control Keys-3 (A/D Input)
I
121
PF3/AN3
OPT1
Logo Mark
I
122
PF4/AN4
Press Sensor
Atmospheric Pressure Sensor
I
123
PF5/AN5
Temp Sensor
Thermistor
I
124
AVSS
GND
A / D Gnd
125
PF6/AN6
POWER FAIL
Power Fail (L : Abnormality)
I
126
PF7/AN7
SDATA IN
SDATA IN
I
127
AVREF
5V
5V A / D REF.
128
AVCC
5V
5V A / D Vcc
129
VSS
Gnd
130
PA0/RXD0
SH_RX
PW365 Rx
I
131
PA1/TXD0
SH_TX
PW365 Tx
O
132
PA2/SCK0/DREQ0/IRQ0
133
PA3/RXD1
Rx
RS232C Rx
I
134
PA4/TXD1
Tx
RS232C Tx
O
135
VCC
5V
136
PA5/SCK1/DREQ1/IRQ1
USB INTR
USB Interrupt Signal Input
Active L
I
137
PE7/TIOC2B
SDA 5
IIC Bus 5 Data
I/O
138
PE8/TIOC3A
SCL 5
IIC Bus 5 Clock
I/O
139
PE9/TIOC3B
SDATA OUT
Single to Dual converter Enhancer Data Output Signal
O
140
PE10/TIOC3C
SCLK
Single to Dual converter Enhancer Clock Output Signal
O
141
VSS
Gnd
142
PE11/TIOC3D
EXP RESET
I/ O Expander
Active H
O
143
PE12/TIOC4A
R/C
R / C Input
Active L
I
144
PE13/TIOC4B/MRES
PW RESET
PW365 Reset Signal
Active L
O
Pin No.
Name
Function Name
Function
Polarity
I/O
CPU and I/O-Expander Control port functions
Summary of Contents for PLC-EF31
Page 63: ... 63 CXA3562R LCD DRIVER FF ...
Page 103: ...Memo ...
Page 104: ...SANYO Electric Co Ltd April 2003 400 Printed in Japan ...