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IC BLOCK DIAGRAM & DESCRIPTION
U0104 SST39VF800(FLASH)
Memory Address
Address Buffer
& Latches
Control Logic
X-Decoder
SuperFlash
Memory
Y-Decoder
I/O Buffer and Data
Latches
DQ
15
-DQ
0
CE#
OE#
WE#
Symbol
Pin Name
Function
To provide memory addresses. During Sector-Erase A
MS
-A
11
address
lines will select the sector. During Block-Erase A
MS
-A
15
address lines will
select the block.
To output data during Read Cycles and receive input data during Write
Cycles.
Data is internally latched during a Write Cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
Unconnected pins
3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39LF200A/400A/800A
Address Inputs
Data Input/output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No connection
AMS
1
-A
0
DQ
15
-DQ
0
CE#
OE#
WE#
V
DD
V
SS
NC
U0105 AT24C02N-10SL-2.7(EEPROM)
1
5
6
7
2
3
4
8
Vcc
GND
WP
SCL
SDA
A
2
A
1
A
0
START
STOP
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
COMP
LOAD
INC
EN
SERIAL
CONTROL
LOGIC
DATA WORD
ADDR/COUNTER
Y DEC
H,V. PUMP/TIMING
E PROM
2
SERIAL MUX
DATA RECOVERY
X DEC
D
OUT
/ACK
LOGIC
D
IN
D
OUT
R/W
