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IC BLOCK DIAGRAM & DESCRIPTION
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
- RA
10
, Column address : CA
0
- CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latchea column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Mskes data output Hi-Z, I
SHZ
sfter the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Pin
CLK
CS
CKE
A
0
- A
10/
AP
BA
RAS
CAS
WE
L(U)DQM
DQ
0
-
15
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Dsta Output Power/Ground
No Connection/
Reserved for Furure Use
Programming Register
Timing Register
Latency & Borst Length
Column Decoder
Data Input Register
Output Buf
fer
Row Decoder
LRAS
LCBR
Bank Select
LRAS
LCAS
LDQM
LWCBR
LCBR
LWE
Row Buf
fer
Refresh Counter
Col. Buf
fer
Address Register
I/O Control
512K x 16
512K x 16
35
20~24,
27~32
2,3,5,6,7,8,9,11,
12,39,40,42,43,
45,46,48,49
35
34
18
17
16
15
36
14
Sense AMP
CLK
ADD
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
DQ1
LDQM
LWE
LCKE
IC822 K4S16162D
(512 X 16Bit X 2 Bank synchronous DRAM )
IC870 LC708746V (6 ch. DAC)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
DVDD
SCKI
BCKIN
LRCIN
DIN0
DIN1
DIN2
MODE
MUTE
LRCIN2
DGND
ML/I2S
MC/IWL
MD/DM
AVDD2
CAP
OUT2L
GR2
OUT2R
AGND1
OUT1L
GR1
OUT1R
AGND2
OUT0L
GR0
OUT0R
AVDD1
Type
Supply
Digital input
Digital input
Digital input
Digital input
Digital input
Digital inpiut
Digital input
Internal pull-up
Digital bidirectional
Digital input
Internal pull-down
Supply
Digital input
Internal pull-up
Digital input
Internal pull-up
Digital input
Supply
Analogue output
Analogue output
Analogue input
Analogue output
Supply
Analogue output
Analogue input
Analogue output
Supply
Analogue output
Analogue input
Analogue output
Supply
Function
Digital power source
System clock input
Audio data bit clock input
Sampling rate clock (LRCK) input
Channel 0 Serial audio data input
Channel 1 Serial audio data inout
Channel 2 Serial audio data input
Control mode select
Low= Software mode
High= Hardware mode
Mute control (PCM mode)
Input
Output (Auto mute active)
Low; Not mute
Low; Mute off
High; Mute
High; Mute on
Z; Auto mute
192kHz/96kHz Mode active 2nd LRCIN input
Digital GND
Software mode; 3way serial control latch lag
Hardware mode; Input format selector
Software mode; 3way serial control clock input
Hardware mode; Input word length select
Software mode; 3way serial control data input
Hardware mode; Deepnhasis select
Analogue power source
Analogue power VREF de-coupling
Lch 2 Output
Ch 2 GND
Rch 2 Output
Analogue GND
Lch 1 Output
Ch 1 GND
Rch 1 Output
Analogue GND
Lch 0 Output
Ch 0 GND
Rch 0 Output
Analogue power source
3
4
10
BCKIN
PDWN
PDWN
PDWN
DEEMPH
UPDA
TE
RxA(23:0)
LxA(23:0)
PL(3:0)
IWL(1:0)
FMT(1:0)
AT
C
PDWN
MUTE
BCP
LRP
LRCIN
LRCIN2
DIN0
DIN1
DIN2
5
6
7
25
26
27
OUT0L
GR0
OUT0R
21
22
23
OUT1L
GR1
OUT1R
17
18
19
OUT2L
GR2
OUT2R
2
SCKI
12
ML/I2S
13
MC/IWL
14
MD/DM
8
MODE
9
MUTE
LC708746V
11
DGND
1
DVDD
20
AGND1
24
AGND2
28
AVDD1
15
AVDD2
16
CAP
Digital
Filter
R0A(7:0)
L1A(7:0)
L0A(7:0)
R1A(7:0)
R2A(7:0)
L2A(7:0)
Stereo
DAC
Sigma
Delta
Modulator
Digital
Filter
AUDIO
INTERFACE
CONTROL
INTERFACE
Stereo
DAC
Sigma
Delta
Modulator
DAC
CHANNEL
CONTOL
Digital
Filter
Stereo
DAC
Sigma
Delta
Modulator
