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IC BLOCK DIAGRAM & DESCRIPTION
IC130 LC78663NRW (DVD/CD Signal Processing)
8
7
5
6
3
4
2
1
19
20
21
33
32
30
31
29
28
27
26
25
24
23
36
43
169~172
167
168
15
16
10
12
13
14
104
11
5
11
6
111
11
2
11
3
11
4
109
11
0
108
134
135
137
139
128
130
129
145~148,150~153, 156~159,161~164
62~65, 68~74
140
141
90
174
173
61
76
142
87
86
85
84
77
75
60
43,
46~52
53~59, 78~82
40
41
42
38
37
94
93
92
91
95
97~103
11
8
11
7
123
124
125
122
121
105
FE
TE
RF-PH
RF-BH
JV
RREC
AD0
AD1
BHC
WO
TEC
FG
EVENT
RFP[3:0]
DEFECTI
DEFECT
O
EFMP
EFMN
SLCO1
SLCO2
SLCLPF0
SLCLPF1
EFMOUT
PISET
FISET
LF1
LF2
LF3
PCN
PPDO
FPDO
VCOCTL
DVDFR
CDFR
PCK
JV
AO
JV
AIN
JVR
VO
JVCPC
JVCPI
XIN
XOUT
X16MIO
DVDCKIO
VPDO
VCOC
VRPFR
HDA
T[7:0]
HADR[12:0]
HRDB
HWRB
HCSB
HW
AITB
HW
AITB
FDO
TDO
SLDO
SPDO
SGC
TBAL
FBAL
BST
FO
TSTDO
TSTDI
TEST
O
HFLIO
EMPH
FSX
EFLG
DOUT
LRSY
ROMCK
ROMXA
C2F
MD[15:0]
MA[10:0]
MRASLB
MRASUB
MCASLB
MOEB
MWEB
AVA
CKO
AV
REQI
A
VDACK
AV
SCTB
AV
E
RRB
A
VD[7:0]
A/D Block
D/A
Block
Servo Block
SLC Block
8 bits
A/D
8 bits
D/A
Servo DSP
(16x16+32
¤
32)
MPX
RF I/F Block
FC Counter
TR Counter
EV Counter
FG Counter
FG Counter
(AD0)
(TEC)
(WO)
(RF BH)
(BHC)
CMP
CMP
CL
V/CA
V Block
BCA
Buf
f Block
SUBCODE I/F Block
EFM PLL
Block
CD Frame Sync
DVD Frame Sync
JV Block
CLK GEN Block
SYS PLL
Block
CPU I/F Block
DVD Dec Block
AV
Dec I/F Block
DRAM I/F Block
CD-ROM Dec Block
CIRC Dec Block
Audio OUT
Block
EMF Block
Frame Synchronous
protection
Frame Synchronous
internal push
EMF demodulation
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NO.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Block
A/D
TEST pin
SLC
TEST pin
Power
supply
CMP
D/A
Power
supply
RF I/F
Microcom-
puter I/F
Power
supply
Block
Microcom-
puter I/F
DRAM I/F
NC
DRAM I/F
Microcom-
puter I/F
CD data
CD data
Pin Name
AD1
AD0
JV
RREC
RF-PH
RF-RH
TE
FE
TEST0
EFMINP
TEST1
EFMINN
SLCLPF0
SLCLPF1
SLCO1
SLCO2
AVDDI
AVSS
BHC
WO
TEC
VREF
TSTD1
TSTD0
FO
BST
TBAL
FBAL
SGC
SLDO
SPDO
TDO
FDO
DVDDO
DVSS
FG
HIRQB
HWAITB
HRESB
HRDB
HWRB
HCSB
HDATO
DVDD1
Pin Name
DVSS
HDAT1
HDAT2
HADT3
HADT4
HDAT5
HDAT6
HADT7
HADR0
HADR1
HADR2
HADR3
HADR4
HADR5
HADR6
MWEB
MRASIB
MA0
MA1
MA2
MA3
NC
NC
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MOEB
MCASUB
MCASLB
HADR7
HADR8
HADR9
HADR10
HADR11
HADR12
C2F
ROMXA
ROMCK
LRSY
DVDD1
DVSS
EMPH
Supplementation
Servo A/D AD1
Servo A/D AD0
Servo A/D JV
Servo A/D RREC
Servo A/D RF-PH
Servo A/D RF-BH
Servo A/D TE
Servo A/D FE
Test input 0
(Input "L" level)
EFM/EFM+ Input
Test input 1
(Input "L" Input)
EFM- Input
SLC
SLC
SLC
SLC
A/D D/A SLC Power source
[Analogue 3.3V]
Analogue GND
Comparator input
(RE-BH)
Comparator input
Comparator input
(TE)
Sarvo D/A Voltage reference
Sarvo D/A
Sarvo D/A TSTD0
Sarvo D/A FO
Sarvo D/A BST
Sarvo D/A TBAL
Sarvo D/A FBAL
Sarvo D/A SGC
Sarvo D/A SLDO
Sarvo D/A SPDO
Sarvo D/A TDO
Sarvo D/A FDO
Internal logic power source
[Digital 2.5V]
Digital GND
FG Counter input General-purpose port in/output
Interrupt signal output
Wait signal output
Servo reset input
Reag reset input
Write signsl input
Chip select signal input
DTA BUS 0
I/O Power source [Digital 3.3V]
Supplementation
Digital GND
Data bus 1
Data bus 2
Data bus 3
Data bus 4
Data bus 5
Data bus 6
Data bus 7
Address bus 0
Address bus 1
Address bus 2
Address bus 3
Address bus 4
Address bus 5
Address bus 6
WE Output
RAS Output I
DRAM Address bus 0
DRAM Address bus 1
DRAM Address bus 2
DRAM Address bus 3
NC pin which set,"H" or "L"
(662; DRAM Power ssupply [Digital 3.3V])
NC pin which set,"H" or "L"
(662;Digital GND)
DRAM Address bus 4
DRAM Address bus 5
DRAM Address bus 6
DRAM Address bus 7
DRAM Address bus 8
DRAM Address bus 9
DRAM Address bus 10
OE Output
CAS Output (Upper Byte)
CAS Output (Lower Byte)
Address bus 7
Address bus 8
Address bus 9
Address bus 10
Address bus 11
Address bus 12
Buffer memory access selector
C2 flag output Monitor pin 4
CD data output Monitor pin 3
CD dast output Monitor pin 2
shift clock output
CD data output L/R clock output Monitor pin 1
I/O power source
Digital GND
Deemphasis monitor pin Monitor pin 0
I/O
I
I
I
I
I
I
I
I
I
I
I
I
-
-
-
-
-
-
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
-
-
I/O
O
I
I
I
I
I
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
O
O
O
O
O
O
-
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
O
O
O
O
-
O
